Datasheet ADE7953 (Analog Devices) - 50

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ADE7953 Data Sheet ADE7953 INTERRUPTS
The ADE7953 interrupts are separated into two groups. The register, but when the RSTIRQSTATA register is accessed, a read- first group of interrupts is associated with the voltage channel with-reset command is executed, clearing the status bits. After and Current Channel A. The second group of interrupts is completion of a read from this register, al status bits are cleared associated with Current Channel B. See Table 22 and Table 24 to 0 and the IRQ pin returns to Logic 1. for a list of the interrupts.
CURRENT CHANNEL B INTERRUPTS
Al interrupts are disabled by default with the exception of the The Current Channel B interrupts are events that occur on RESET interrupt that is located within the group of primary Current Channel B. Like the primary group of interrupts, interrupts. This interrupt is enabled by default and signals the Current Channel B interrupts are handled by a group of three end of a software or hardware reset. On power-up, this interrupt registers: the enable register, IRQENB (Address 0x22F and is triggered to signal that the ADE7953 is ready to receive Address 0x32F), the status register, IRQSTATB (Address 0x230 communication from the microcontrol er. This interrupt should and Address 0x330), and the reset status register, RSTIRQSTATB be serviced as described in the Primary Interrupts (Voltage (Address 0x231 and Address 0x331). The bits in these registers Channel and Current Channel A) section prior to configuring are described in Table 24 and Table 25. the ADE7953.
PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND
When an interrupt event occurs, the corresponding bit in the IRQSTATB register is set to 1. The Current Channel B
CURRENT CHANNEL A)
interrupts do not have a dedicated output pin. This function The primary interrupts are events that occur on the voltage can be configured as an alternative output on Pin 1 (ZX), channel and Current Channel A. These interrupts are handled Pin 21 (ZX_I), or Pin 20 (REVP) (see the Alternative Output by a group of three registers: the enable register, IRQENA Functions section). If an output is enabled for interrupt events (Address 0x22C and Address 0x32C), the status register, on Current Channel B and the interrupt enable bit, located in IRQSTATA (Address 0x22D and Address 0x32D), and the the IRQENB register, is set to 1, Pin 1, Pin 21, or Pin 20 is reset status register, RSTIRQSTATA (Address 0x22E and pul ed low if an interrupt event occurs on Current Channel B. Address 0x32E). The bits in these registers are described in The status bits located in the IRQSTATB register are set when Table 22 and Table 23. an interrupt event occurs, regardless of whether an external When an interrupt event occurs, the corresponding bit in the interrupt output is enabled. IRQSTATA register is set to 1. If the enable bit for this interrupt, Al interrupts are latched and require servicing to clear. To located in the IRQENA register, is set to 1, the external IRQ pin service the interrupt, the status bits must be cleared using the is pul ed to Logic 0. The status bits located in the IRQSTATA RSTIRQSTATB register (Address 0x231 and Address 0x331). register are set when an interrupt event occurs, regardless of The RSTIRQSTATB register contains the same interrupt status whether the external interrupt is enabled. bits as the IRQSTATB register, but when the RSTIRQSTATB Al interrupts are latched and require servicing to clear. To register is accessed, a read-with-reset command is executed, service the interrupt and return the IRQ pin to Logic 1, the clearing the status bits. After completion of a read from this status bits must be cleared using the RSTIRQSTATA register register, al status bits are cleared to 0 and the appropriate (Address 0x22E and Address 0x32E). The RSTIRQSTATA output pin (if enabled) returns to Logic 1. register contains the same interrupt status bits as the IRQSTATA Rev. C | Page 50 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS SPI Interface Timing SPI Interface Timing Diagram I2C Interface Timing I2C Interface Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY ADE7953 POWER-UP PROCEDURE REQUIRED REGISTER SETTING THEORY OF OPERATION ANALOG INPUTS Current Channel A Current Channel B Voltage Channel ANALOG-TO-DIGITAL CONVERSION Oversampling Noise Shaping Antialiasing Filter CURRENT CHANNEL ADCS di/dt Current Sensor and Digital Integrator VOLTAGE CHANNEL ADC REFERENCE CIRCUIT ROOT MEAN SQUARE MEASUREMENT CURRENT CHANNEL RMS CALCULATION VOLTAGE CHANNEL RMS CALCULATION ACTIVE POWER CALCULATION SIGN OF ACTIVE POWER CALCULATION ACTIVE ENERGY CALCULATION Active Energy Integration Time Under Steady Load Active Energy Line Cycle Accumulation Mode ACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Positive-Only Accumulation Mode Absolute Accumulation Mode REACTIVE POWER CALCULATION SIGN OF REACTIVE POWER CALCULATION REACTIVE ENERGY CALCULATION Reactive Energy Integration Time Under Steady Load Reactive Energy Line Cycle Accumulation Mode REACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Antitamper Accumulation Mode Absolute Accumulation Mode APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Apparent Energy Integration Time Under Steady Load Apparent Energy Line Cycle Accumulation Mode AMPERE-HOUR ACCUMULATION ENERGY-TO-FREQUENCY CONVERSION PULSE OUTPUT CHARACTERISTICS ENERGY CALIBRATION GAIN CALIBRATION Current Channel Gain Adjustment PHASE CALIBRATION OFFSET CALIBRATION Power Offsets RMS Offsets PERIOD MEASUREMENT INSTANTANEOUS POWERS AND WAVEFORM SAMPLING POWER FACTOR USING THE LINE CYCLE ACCUMULATION MODE TO DETERMINE THE POWER FACTOR POWER FACTOR WITH NO-LOAD DETECTION ANGLE MEASUREMENT NO-LOAD DETECTION SETTING THE NO-LOAD THRESHOLDS ACTIVE ENERGY NO-LOAD DETECTION Active Energy No-Load Interrupt Active Energy No-Load Status Bits REACTIVE ENERGY NO-LOAD DETECTION Reactive Energy No-Load Interrupt Reactive Energy No-Load Status Bits APPARENT ENERGY NO-LOAD DETECTION Apparent Energy No-Load Interrupt Apparent Energy No-Load Status Bits ZERO-CROSSING DETECTION ZERO-CROSSING OUTPUT PINS Voltage Channel Zero Crossing Current Channel Zero Crossing ZERO-CROSSING INTERRUPTS ZERO-CROSSING TIMEOUT ZERO-CROSSING THRESHOLD VOLTAGE SAG DETECTION SETTING THE SAGCYC REGISTER SETTING THE SAGLVL REGISTER VOLTAGE SAG INTERRUPT PEAK DETECTION INDICATION OF POWER DIRECTION REVERSE POWER SIGN INDICATION OVERCURRENT AND OVERVOLTAGE DETECTION SETTING THE OVLVL AND OILVL REGISTERS OVERVOLTAGE AND OVERCURRENT INTERRUPTS ALTERNATIVE OUTPUT FUNCTIONS ADE7953 INTERRUPTS PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND CURRENT CHANNEL A) CURRENT CHANNEL B INTERRUPTS COMMUNICATING WITH THE ADE7953 COMMUNICATION AUTODETECTION LOCKING THE COMMUNICATION INTERFACE SPI INTERFACE I2C INTERFACE I2C Write Operations I2C Read Operations UART INTERFACE UART Read UART Write COMMUNICATION VERIFICATION AND SECURITY WRITE PROTECTION COMMUNICATION VERIFICATION CHECKSUM REGISTER ADE7953 REGISTERS ADE7953 REGISTER DESCRIPTIONS Interrupt Enable and Interrupt Status Registers Current Channel A and Voltage Channel Registers Current Channel B Registers LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE