Datasheet ADE7953 (Analog Devices) - 55

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Data Sheet ADE7953 UART INTERFACE Table 10. Frames in the UART Packet
The ADE7953 provides a simple universal asynchronous
Frame Function
receiver/transmit er (UART) interface that allows al the functions F1 Read/write of the ADE7953 to be accessed using only two single-direction F2 Address MSB pins. The UART interface al ows an isolated communication F3 Address LSB interface to be achieved using only two low cost opto-isolators. F1 determines whether the communication is a read or a write The UART interface operates at a fixed baud rate of 4800 bps operation, and the following two frames (F2 and F3) select the and is therefore suitable for low speed designs. register that is to be accessed. Each frame consists of eight data The UART interface on the ADE7953 is accessed via the Tx pin bits, as shown in Figure 72. A read is issued by writing the value (Pin 26), which transmits data from the ADE7953, and the Rx 0x35 to F1, and a write is issued by writing the value 0xCA to pin (Pin 27), which receives data from the microcontrol er. A F1. Any other value is interpreted as invalid and results in an simple master/slave topology is implemented on the UART inter- unsuccessful communication with the ADE7953. The address face with the ADE7953 acting as the slave. Al communication bytes are sent MSB first; therefore, F2 contains the most is initiated by the sending of a valid frame by the master (the significant portion of the address, and F3 contains the least microcontroller) to the slave (the ADE7953). The format of the significant portion of the address. The bits within each address frame is shown in Figure 72. frame are sent LSB first. As shown in Figure 72, each frame consists of 10 bits. Each bit is The ADE7953 UART interface uses two timeouts, t1 and t2, to sent at a bit rate of 4800 bps, resulting in a frame time of 2.08 ms synchronize the communication and to prevent the communi- ((1/4800) × 10). A wait period of 6 ms should be added from cation from halting. The first timeout, t1, is the frame-to-frame when the UART communication mode is established using the delay and is fixed at 4 ms max. The second timeout, t2, is the CS and SCLK pins to when the first frame is sent. A minimum packet-to-packet delay and is fixed at 6 ms min. These two wait of 0.2 ms should be included between frames. Al frame timeouts act as a reset for the UART function. More informa- data is sent LSB first. tion about how the timeouts are implemented is provided in the UART Read section and the UART Write section. Communication via the UART interface is initiated by the master sending a packet of three frames (see Table 10). Verification of a successful UART communication can be achieved by implementing a write/read/verify sequence in the microcontroller. Successful communications are also recorded in the LAST_ADD, LAST_RWDATA, and LAST_OP registers, as described in the Communication Verification section.
t2 SCLK CS t1 P Rx ART O ART T D0 D1 D2 D3 D4 D5 D6 D7 T T D0 S S S FRAME t1 = FRAME DELAY: 0.2ms (MIN), 4ms (MAX)
141
t2 = PACKET DELAY: 6ms (MIN)
09320- Figure 72. UART Frame Rev. C | Page 55 of 72 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS SPI Interface Timing SPI Interface Timing Diagram I2C Interface Timing I2C Interface Timing Diagram ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT TERMINOLOGY ADE7953 POWER-UP PROCEDURE REQUIRED REGISTER SETTING THEORY OF OPERATION ANALOG INPUTS Current Channel A Current Channel B Voltage Channel ANALOG-TO-DIGITAL CONVERSION Oversampling Noise Shaping Antialiasing Filter CURRENT CHANNEL ADCS di/dt Current Sensor and Digital Integrator VOLTAGE CHANNEL ADC REFERENCE CIRCUIT ROOT MEAN SQUARE MEASUREMENT CURRENT CHANNEL RMS CALCULATION VOLTAGE CHANNEL RMS CALCULATION ACTIVE POWER CALCULATION SIGN OF ACTIVE POWER CALCULATION ACTIVE ENERGY CALCULATION Active Energy Integration Time Under Steady Load Active Energy Line Cycle Accumulation Mode ACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Positive-Only Accumulation Mode Absolute Accumulation Mode REACTIVE POWER CALCULATION SIGN OF REACTIVE POWER CALCULATION REACTIVE ENERGY CALCULATION Reactive Energy Integration Time Under Steady Load Reactive Energy Line Cycle Accumulation Mode REACTIVE ENERGY ACCUMULATION MODES Signed Accumulation Mode Antitamper Accumulation Mode Absolute Accumulation Mode APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Apparent Energy Integration Time Under Steady Load Apparent Energy Line Cycle Accumulation Mode AMPERE-HOUR ACCUMULATION ENERGY-TO-FREQUENCY CONVERSION PULSE OUTPUT CHARACTERISTICS ENERGY CALIBRATION GAIN CALIBRATION Current Channel Gain Adjustment PHASE CALIBRATION OFFSET CALIBRATION Power Offsets RMS Offsets PERIOD MEASUREMENT INSTANTANEOUS POWERS AND WAVEFORM SAMPLING POWER FACTOR USING THE LINE CYCLE ACCUMULATION MODE TO DETERMINE THE POWER FACTOR POWER FACTOR WITH NO-LOAD DETECTION ANGLE MEASUREMENT NO-LOAD DETECTION SETTING THE NO-LOAD THRESHOLDS ACTIVE ENERGY NO-LOAD DETECTION Active Energy No-Load Interrupt Active Energy No-Load Status Bits REACTIVE ENERGY NO-LOAD DETECTION Reactive Energy No-Load Interrupt Reactive Energy No-Load Status Bits APPARENT ENERGY NO-LOAD DETECTION Apparent Energy No-Load Interrupt Apparent Energy No-Load Status Bits ZERO-CROSSING DETECTION ZERO-CROSSING OUTPUT PINS Voltage Channel Zero Crossing Current Channel Zero Crossing ZERO-CROSSING INTERRUPTS ZERO-CROSSING TIMEOUT ZERO-CROSSING THRESHOLD VOLTAGE SAG DETECTION SETTING THE SAGCYC REGISTER SETTING THE SAGLVL REGISTER VOLTAGE SAG INTERRUPT PEAK DETECTION INDICATION OF POWER DIRECTION REVERSE POWER SIGN INDICATION OVERCURRENT AND OVERVOLTAGE DETECTION SETTING THE OVLVL AND OILVL REGISTERS OVERVOLTAGE AND OVERCURRENT INTERRUPTS ALTERNATIVE OUTPUT FUNCTIONS ADE7953 INTERRUPTS PRIMARY INTERRUPTS (VOLTAGE CHANNEL AND CURRENT CHANNEL A) CURRENT CHANNEL B INTERRUPTS COMMUNICATING WITH THE ADE7953 COMMUNICATION AUTODETECTION LOCKING THE COMMUNICATION INTERFACE SPI INTERFACE I2C INTERFACE I2C Write Operations I2C Read Operations UART INTERFACE UART Read UART Write COMMUNICATION VERIFICATION AND SECURITY WRITE PROTECTION COMMUNICATION VERIFICATION CHECKSUM REGISTER ADE7953 REGISTERS ADE7953 REGISTER DESCRIPTIONS Interrupt Enable and Interrupt Status Registers Current Channel A and Voltage Channel Registers Current Channel B Registers LAYOUT GUIDELINES OUTLINE DIMENSIONS ORDERING GUIDE