Datasheet LT1468 (Analog Devices) - 10

LT1468
APPLICATIONS INFORMATION
The LT1468 may be inserted directly into many operational contacts to the inputs can exceed the inherent drift of amplifi er applications improving both DC and AC perfor- the amplifi er. Air currents over device leads should be mance, provided that the nulling circuitry is removed. minimized, package leads should be short, and the two The suggested nulling circuit for the LT1468 is shown input leads should be as close together as possible and below. maintained at the same temperature.
Offset Nulling
Make no connection to Pin 8. This pin is used for factory trim of the inverting input current. V+ The parallel combination of the feedback resistor and gain 3 + 0.1μF 2.2μF 7 setting resistor on the inverting input can combine with the 6 LT1468 input capacitance to form a pole that can cause peaking 2 4 – or even oscillations. For feedback resistors greater than 5 1 0.1μF 2.2μF 2k, a feedback capacitor of the value: 100k C V– 1468 AI01 F > (RG)(CIN/RF) should be used to cancel the input pole and optimize dy- namic performance. For applications where the DC noise
Layout and Passive Components
gain is one, and a large feedback resistor is used, CF should The LT1468 requires attention to detail in board layout be greater than or equal to CIN. An example would be a in order to maximize DC and AC performance. For best DAC I-to-V converter as shown on the front page of this AC results (for example fast settling time) use a ground data sheet where the DAC can have many tens of pF of plane, short lead lengths, and RF-quality bypass capacitors output capacitance. Another example would be a gain of –1 (0.01μF to 0.1μF) in parallel with low ESR bypass capaci- with 5k resistors; a 5pF to 10pF capacitor should be added tors (1μF to 10μF tantalum). For best DC performance, use across the feedback resistor. The frequency response in a “star” grounding techniques, equalize input trace lengths gain of –1 is shown in the Typical Performance curves with and minimize leakage (i.e., 1.5GΩ of leakage between an 2k and 5.1k resistors with a 5pF feedback capacitor. input and a 15V supply will generate 10nA—equal to the maximum I – B specifi cation.)
Nulling Input Capacitance
Board leakage can be minimized by encircling the input circuitry with a guard ring operated at a potential close RF to that of the inputs. For inverting confi gurations tie the CF ring to ground, in noninverting connections tie the ring to the inverting input (note the input capacitance will RG – increase which may require a compensating capacitor as C LT1468 V discussed below.) IN OUT VIN + Microvolt level error voltages can also be generated in 1468 AI02 the external circuitry. Thermocouple effects caused by temperature gradients across dissimilar metals at the 1468fb 10