Datasheet ADP5052 (Analog Devices) - 34

ADP5052 Data Sheet ADP5052 VREG VREG SYNC/MODE INT VREG C1 VDD OSCILLATOR 100mA RT 31.6kΩ 1.0µF C0 1.0µF 10kΩ FB1 PVIN1 4.99kΩ 12V BST1 SW1 C2 C3 CHANNEL 1 0.1µF L1 10µF VOUT1 1.2V/8A COMP1 BUCK REGULATOR (1.2A/2.5A/4A) 1.5µH 2.7nF 5V REG 10kΩ C4 C16 Si7232DN 100µF 100µF EN1 (16.4mΩ) Q1 DL1 VREG 100kΩ SS12 22kΩ PGND 600kΩ 22kΩ DL2 Q2 C5 PVIN2 10µF CHANNEL 2 5V REG L2 SW2 BUCK REGULATOR COMP2 (1.2A/2.5A/4A) 1.5µH C6 BST2 0.1µF EN2 FB2 PWRGD PVIN3 BST3 C8 C9 0.1µF L3 10µF SW3 VOUT3 1.5V/1.2A COMP3 CHANNEL 3 2.7nF BUCK REGULATOR 6.8µH 6.81kΩ C10 (1.2A) FB3 22µF EN3 10.2kΩ 8.87kΩ PGND3 VREG SS34 BST4 PVIN4 C12 0.1µF L4 3.3V/1.2A SW4 VOUT4 C11 CHANNEL 4 10µF 10µH BUCK REGULATOR COMP4 C13 (1.2A) FB4 22µF 2.7nF 6.81kΩ 10.2kΩ 31.6kΩ PGND4 EN4 C14 1µF PVIN5 CHANNEL 5 VOUT5 EN5 200mA LDO REGULATOR FB5 40.2kΩ C15 VOUT5 2.5V/200mA 10kΩ 1µF EXPOSED PAD
165 10900- Figure 56. Typical Channel 1/Channel 2 Parallel Output Application, 600 kHz Switching Frequency, Adjustable Output Model Rev. D | Page 34 of 36 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN LDO REGULATOR APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE