Datasheet ADSP-BF592 (Analog Devices) - 32

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ADSP-BF592 Serial Peripheral Interface (SPI) Port—Slave Timing
Table 27 and Figure 20 describe SPI port slave operations.
Table 27. Serial Peripheral Interface (SPI) Port—Slave Timing VDDEXT VDDEXT 1.8V Nominal 2.5 V/3.3V Nominal Parameter Min Max Min Max Unit
Timing Requirements tSPICHS Serial Clock High Period 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns tSPICLS Serial Clock Low Period 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns tSPICLK Serial Clock Period 4 × tSCLK 4 × tSCLK ns tHDS Last SCK Edge to SPI_SS Not Asserted 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns tSPITDS Sequential Transfer Delay 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns tSDSCI SPI_SS Assertion to First SCK Edge 2 × tSCLK – 1.5 2 × tSCLK – 1.5 ns tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6 1.6 ns tHSPID SCK Sampling Edge to Data Input Invalid 2 1.6 ns Switching Characteristics tDSOE SPI_SS Assertion to Data Out Active 0 12 0 10.3 ns tDSDHI SPI_SS Deassertion to Data High Impedance 0 11 0 9 ns tDDSPID SCK Edge to Data Out Valid (Data Out Delay) 10 10 ns tHDSPID SCK Edge to Data Out Invalid (Data Out Hold) 0 0 ns
SPIxSS (INPUT) tSDSCI tSPICLS tSPICHS tSPICLK tHDS tSPITDS SPIxSCK (INPUT) tDSOE tDDSPID tHDSPID tDDSPID tDSDHI SPIxMISO (OUTPUT) CPHA = 1 tSSPID tHSPID SPIxMOSI (INPUT) tDSOE tHDSPID tDDSPID tDSDHI SPIxMISO (OUTPUT) tHSPID CPHA = 0 tSSPID SPIxMOSI (INPUT)
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. B | Page 32 of 44 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Core Memory Architecture Internal (Core-Accessible) Memory L1 Utility ROM Custom ROM (Optional) I/O Memory Space Booting from ROM Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) DMA Controllers Processor Peripherals Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Port Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions ITU-R 656 Mode Descriptions TWI Controller Interface Ports General-Purpose I/O (GPIO) Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Signal Descriptions Specifications Operating Conditions ADSP-BF592 Clock Related Operating Conditions Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 64-Lead LFCSP Lead Assignment Outline Dimensions Automotive Products Ordering Guide