Datasheet ADAU1701 (Analog Devices) - 6

ADAU1701 Data Sheet DIGITAL INPUT/OUTPUT Table 2. Parameter Symbol Min Typ Max1 Unit Test Conditions/Comments
Input Voltage, High VIH 2.0 IOVDD V Input Voltage, Low VIL 0.8 V Input Leakage, High IIH 1 µA Excluding MCLKI Input Leakage, Low IIL 1 µA Excluding MCLKI and bidirectional pins Bidirectional Pin Pull-Up Current, Low 150 µA MCLKI Input Leakage, High IIH 3 µA MCLKI Input Leakage, Low IIL 3 µA High Level Output Voltage VOH 2.0 V IOH = 2 mA Low Level Output Voltage VOL 0.8 V IOL = 2 mA Input Capacitance 5 pF GPIO Output Drive 2 mA 1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
POWER Table 3. Parameter Min Typ Max1 Unit
SUPPLY VOLTAGE Analog Voltage 3.3 V Digital Voltage 1.8 V PLL Voltage 3.3 V IOVDD Voltage 3.3 V SUPPLY CURRENT Analog Current (AVDD and PVDD) 50 85 mA Digital Current (DVDD) 40 60 mA Analog Current, Reset 35 55 mA Digital Current, Reset 1.5 4.5 mA DISSIPATION Operation (AVDD, DVDD, PVDD)2 286.5 mW Reset, All Supplies 118 mW POWER SUPPLY REJECTION RATIO (PSRR) 1 kHz, 200 mV p-p Signal at AVDD 50 dB 1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V. 2 Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
TEMPERATURE RANGE Table 4. Parameter Min Typ Max Unit
Functionality Guaranteed 0 70 °C ambient
PLL AND OSCILLATOR Table 5. PLL and Oscillator1 Parameter Min Typ Max Unit
PLL Operating Range MCLK_Nom − 20% MCLK_Nom + 20% MHz PLL Lock Time 20 ms Crystal Oscillator Transconductance (gm) 78 mmho 1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V. Rev. C | Page 6 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE DIGITAL INPUT/OUTPUT POWER TEMPERATURE RANGE PLL AND OSCILLATOR REGULATOR DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION INITIALIZATION POWER-UP SEQUENCE CONTROL REGISTERS SETUP DSP Core Control Register (Address 2076) DAC Setup Register (Address 2087) RECOMMENDED PROGRAM/PARAMETER LOADING PROCEDURE POWER REDUCTION MODES USING THE OSCILLATOR SETTING MASTER CLOCK/PLL MODE VOLTAGE REGULATOR AUDIO ADCs AUDIO DACs CONTROL PORTS I2C PORT Addressing I2C Read and Write Operations SPI PORT Chip Address R/ Subaddress Data Bytes SELF-BOOT EEPROM Format Writeback SIGNAL PROCESSING NUMERIC FORMATS Numerical Format: 5.23 PROGRAMMING RAMS AND REGISTERS ADDRESS MAPS PARAMETER RAM Direct Read/Write Safeload Write DATA RAM READ/WRITE DATA FORMATS CONTROL REGISTER MAP CONTROL REGISTER DETAILS 2048 TO 2055 (0x0800 TO 0x0807)—INTERFACE REGISTERS 2056 (0x0808)—GPIO PIN SETTING REGISTER 2057 TO 2060 (0x0809 TO 0x080C)—AUXILIARY ADC DATA REGISTERS 2064 TO 2068 (0x0810 TO 0x0814)—SAFELOAD DATA REGISTERS 2069 TO 2073 (0x0815 TO 0x819)—SAFELOAD ADDRESS REGISTERS 2074 TO 2075 (0x081A TO 0x081B)—DATA CAPTURE REGISTERS 2076 (0x081C)—DSP CORE CONTROL REGISTER 2078 (0x081E)—SERIAL OUTPUT CONTROL REGISTER 2079 (0x081F)—SERIAL INPUT CONTROL REGISTER 2080 TO 2081 (0x0820 TO 0x0821)—MULTIPURPOSE PIN CONFIGURATION REGISTERS 2082 (0x0822)—AUXILIARY ADC AND POWER CONTROL 2084 (0x0824)—AUXILIARY ADC ENABLE 2086 (0x0826)—OSCILLATOR POWER-DOWN 2087 (0x0827)—DAC SETUP MULTIPURPOSE PINS AUXILIARY ADC GENERAL-PURPOSE INPUT/OUTPUT PINS SERIAL DATA INPUT/OUTPUT PORTS LAYOUT RECOMMENDATIONS PARTS PLACEMENT GROUNDING TYPICAL APPLICATION SCHEMATICS SELF-BOOT MODE I2C CONTROL SPI CONTROL OUTLINE DIMENSIONS ORDERING GUIDE