Datasheet CMX655A, CMX655D (CML Microcircuits) - 3
| Fabricante | CML Microcircuits |
| Descripción | Ultra Low Power Voice Codec |
| Páginas / Página | 79 / 3 — Contents. Brief Description ... 2. Block Diagram .. 7. Pin List .. 8. … |
| Revisión | 3 |
| Formato / tamaño de archivo | PDF / 2.6 Mb |
| Idioma del documento | Inglés |
Contents. Brief Description ... 2. Block Diagram .. 7. Pin List .. 8. External Components ... 14. General Description .. 22
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Contents
Section Page
1 Brief Description ... 2 2 Block Diagram .. 7
2.1 CMX655A ... 7 2.2 CMX655D ... 7
3 Pin List .. 8
3.1 CMX655A ... 8 3.2 CMX655D ... 11
4 External Components ... 14
4.1 CMX655A ... 14 4.1.1 Power Supply and Pin Decoupling ... 14 4.1.2 SPI .. 15 4.1.3 TWI .. 16 4.1.4 Speaker and Microphone .. 17 4.2 CMX655D ... 18 4.2.1 Power Supply and Pin Decoupling ... 18 4.2.2 SPI .. 19 4.2.3 TWI .. 20 4.2.4 Speaker and Microphone .. 21
5 General Description .. 22
5.1 Power Management .. 22 5.1.1 External Supplies ... 22 5.1.2 Regulated Supplies .. 22 5.2 Device Reset .. 22 5.2.1 Power-On-Reset .. 22 5.2.2 Reset Pin .. 22 5.3 Main Clock ... 23 5.3.1 Clock Frequency .. 23 5.3.2 Clock Generation ... 23 5.3.3 PLL ... 24 5.3.4 Low Power Oscillator ... 25 5.3.5 Clock Control Registers .. 25 5.4 Microphone Interface ... 26 5.4.1 Digital Microphone Interface .. 26 5.4.2 Analogue Microphone Interface ... 27 5.5 Class-D Amplifier ... 29 5.5.1 Audio Outputs ... 29 5.5.2 Overload Current Protection ... 29 5.5.3 Thermal Protection.. 29 5.5.4 Clipping Detection ... 29 5.6 Audio Signal Processing ... 29 5.6.1 Record Level Control ... 29 5.6.2 Automatic Gain Control ... 30 5.6.3 Noise Gate ... 32 5.6.4 Record Level Detection ... 35 5.6.5 Playback Preamplifier Gain .. 36 5.6.6 Playback Volume Control .. 37 5.6.7 Automatic Level Control .. 38 5.6.8 Digital Sidetone ... 40 5.6.9 Voice Filters ... 41 5.6.10 Channel Multiplexing .. 43 5.6.11 Click-and-Pop Reduction ... 43 5.7 Control Interface ... 43 5.7.1 SPI Slave .. 44 5.7.2 TWI Slave ... 45 5.8 Serial Audio Interface .. 48 5.8.1 I2S Mode ... 48 5.8.2 Left-Justified Mode.. 48 5.8.3 PCM Mode ... 49 5.8.4 Audio Companding .. 50 2018 CML Microsystems Plc 3 D/655/3 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655A 2.2 CMX655D 3 Pin List 3.1 CMX655A 3.2 CMX655D 4 External Components 4.1 CMX655A 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 4.2 CMX655D 4.2.1 Power Supply and Pin Decoupling 4.2.2 SPI 4.2.3 TWI 4.2.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.4.2 Analogue Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Automatic Gain Control 5.6.2.1 AGC Registers 5.6.3 Noise Gate 5.6.3.1 Noise Gate Registers 5.6.4 Record Level Detection 5.6.4.1 Record Level Detection Registers 5.6.5 Playback Preamplifier Gain 5.6.5.1 Playback Preamplifier Gain Register 5.6.6 Playback Volume Control 5.6.6.1 Playback Volume Register 5.6.7 Automatic Level Control 5.6.7.1 ALC Registers 5.6.8 Digital Sidetone 5.6.8.1 Digital Sidetone Register 5.6.9 Voice Filters 5.6.9.1 Low Pass Filter 5.6.9.2 DC Blocking Filter 5.6.9.3 High Pass Filter 5.6.9.4 Voice Filters Registers 5.6.10 Channel Multiplexing 5.6.11 Click-and-Pop Reduction 5.6.11.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 DC-offset Calibration 6.1.3 Configuration 6.1.4 Enable Audio Channels 6.1.5 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D/CMX655A End of Document
Contents
Section Page
1 Brief Description ... 2 2 Block Diagram .. 7
2.1 CMX655A ... 7 2.2 CMX655D ... 7
3 Pin List .. 8
3.1 CMX655A ... 8 3.2 CMX655D ... 11
4 External Components ... 14
4.1 CMX655A ... 14 4.1.1 Power Supply and Pin Decoupling ... 14 4.1.2 SPI .. 15 4.1.3 TWI .. 16 4.1.4 Speaker and Microphone .. 17 4.2 CMX655D ... 18 4.2.1 Power Supply and Pin Decoupling ... 18 4.2.2 SPI .. 19 4.2.3 TWI .. 20 4.2.4 Speaker and Microphone .. 21
5 General Description .. 22
5.1 Power Management .. 22 5.1.1 External Supplies ... 22 5.1.2 Regulated Supplies .. 22 5.2 Device Reset .. 22 5.2.1 Power-On-Reset .. 22 5.2.2 Reset Pin .. 22 5.3 Main Clock ... 23 5.3.1 Clock Frequency .. 23 5.3.2 Clock Generation ... 23 5.3.3 PLL ... 24 5.3.4 Low Power Oscillator ... 25 5.3.5 Clock Control Registers .. 25 5.4 Microphone Interface ... 26 5.4.1 Digital Microphone Interface .. 26 5.4.2 Analogue Microphone Interface ... 27 5.5 Class-D Amplifier ... 29 5.5.1 Audio Outputs ... 29 5.5.2 Overload Current Protection ... 29 5.5.3 Thermal Protection.. 29 5.5.4 Clipping Detection ... 29 5.6 Audio Signal Processing ... 29 5.6.1 Record Level Control ... 29 5.6.2 Automatic Gain Control ... 30 5.6.3 Noise Gate ... 32 5.6.4 Record Level Detection ... 35 5.6.5 Playback Preamplifier Gain .. 36 5.6.6 Playback Volume Control .. 37 5.6.7 Automatic Level Control .. 38 5.6.8 Digital Sidetone ... 40 5.6.9 Voice Filters ... 41 5.6.10 Channel Multiplexing .. 43 5.6.11 Click-and-Pop Reduction ... 43 5.7 Control Interface ... 43 5.7.1 SPI Slave .. 44 5.7.2 TWI Slave ... 45 5.8 Serial Audio Interface .. 48 5.8.1 I2S Mode ... 48 5.8.2 Left-Justified Mode.. 48 5.8.3 PCM Mode ... 49 5.8.4 Audio Companding .. 50 2018 CML Microsystems Plc 3 D/655/3 Document Outline Datasheet Front Page 1 Brief Description 2 Block Diagram 2.1 CMX655A 2.2 CMX655D 3 Pin List 3.1 CMX655A 3.2 CMX655D 4 External Components 4.1 CMX655A 4.1.1 Power Supply and Pin Decoupling 4.1.2 SPI 4.1.3 TWI 4.1.4 Speaker and Microphone 4.2 CMX655D 4.2.1 Power Supply and Pin Decoupling 4.2.2 SPI 4.2.3 TWI 4.2.4 Speaker and Microphone 5 General Description 5.1 Power Management 5.1.1 External Supplies 5.1.2 Regulated Supplies 5.2 Device Reset 5.2.1 Power-On-Reset 5.2.2 Reset Pin 5.3 Main Clock 5.3.1 Clock Frequency 5.3.2 Clock Generation 5.3.3 PLL 5.3.4 Low Power Oscillator 5.3.5 Clock Control Registers 5.3.5.1 CLKCTRL ($03) 5.3.5.2 RDIVHI ($04) 5.3.5.3 RDIVLO ($05) 5.3.5.4 NDIVHI ($06) 5.3.5.5 NDIVLO ($07) 5.3.5.6 PLLCTRL ($08) 5.4 Microphone Interface 5.4.1 Digital Microphone Interface 5.4.2 Analogue Microphone Interface 5.5 Class-D Amplifier 5.5.1 Audio Outputs 5.5.2 Overload Current Protection 5.5.3 Thermal Protection 5.5.4 Clipping Detection 5.6 Audio Signal Processing 5.6.1 Record Level Control 5.6.1.1 Record Level Control Register 5.6.2 Automatic Gain Control 5.6.2.1 AGC Registers 5.6.3 Noise Gate 5.6.3.1 Noise Gate Registers 5.6.4 Record Level Detection 5.6.4.1 Record Level Detection Registers 5.6.5 Playback Preamplifier Gain 5.6.5.1 Playback Preamplifier Gain Register 5.6.6 Playback Volume Control 5.6.6.1 Playback Volume Register 5.6.7 Automatic Level Control 5.6.7.1 ALC Registers 5.6.8 Digital Sidetone 5.6.8.1 Digital Sidetone Register 5.6.9 Voice Filters 5.6.9.1 Low Pass Filter 5.6.9.2 DC Blocking Filter 5.6.9.3 High Pass Filter 5.6.9.4 Voice Filters Registers 5.6.10 Channel Multiplexing 5.6.11 Click-and-Pop Reduction 5.6.11.1 Click-and-Pop Reduction Register 5.7 Control Interface 5.7.1 SPI Slave 5.7.2 TWI Slave 5.8 Serial Audio Interface 5.8.1 I2S Mode 5.8.2 Left-Justified Mode 5.8.3 PCM Mode 5.8.4 Audio Companding 5.8.5 Serial Audio Interface Registers 5.9 Interrupt Status and IRQN Pin 5.9.1 Interrupt Registers 5.10 System Control 5.10.1 System Control Registers 5.11 Register Address Map 6 Application Notes 6.1 Programming Examples 6.1.1 Start-up 6.1.2 DC-offset Calibration 6.1.3 Configuration 6.1.4 Enable Audio Channels 6.1.5 Shutdown 7 Performance Specification 7.1 Electrical Performance 7.1.1 Absolute Maximum Ratings 7.1.2 Operating Limits 7.1.3 Operating Characteristics 7.1.3.1 DC Parameters 7.1.3.2 AC Parameters 7.1.3.3 SPI 7.1.3.4 TWI 7.1.3.5 SAI 7.1.3.6 Digital Microphone Interface 7.2 Typical Performance Characteristics 7.2.1 THD+N vs. Level performance 7.2.2 THD+N vs. Frequency performance 7.2.3 Class D Amplifier Efficiency 7.2.4 Filter Performance Speaker Channel 7.2.5 Filter Performance Microphone Channel 7.3 Packaging 7.3.1 CMX655D/CMX655A End of Document