Datasheet IM231-M6S1B / IM231-M6T2B (Infineon) - 6
| Fabricante | Infineon |
| Descripción | 600 V three-phase Intelligent Power Module |
| Páginas / Página | 24 / 6 — CIPOS™ Micro. IM231-M6S1B / IM231-M6T2B. Figure 5. Typical PCB circuit … |
| Revisión | 02_00 |
| Formato / tamaño de archivo | PDF / 1.4 Mb |
| Idioma del documento | Inglés |
CIPOS™ Micro. IM231-M6S1B / IM231-M6T2B. Figure 5. Typical PCB circuit connected to. the RFE pin. Figure 6
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CIPOS™ Micro IM231-M6S1B / IM231-M6T2B
Pin Configuration VRFE(t) = 3.3V * e-t/RC < VIN,TH- +3.3V CRCIN < 500ns / ( - ln (VIN,TH- / 3.3V) * RRFE_ON) Consider VIN,TH- of 0.8V and RRFE_ON of 50ohm, CRCIN RRCIN 6 L- should be less than 7nF. It is also suggested to use a 1 To Microcontroller 3 2 RRCIN of between 0.5MΩ and 2MΩ. 6 RFE IM CRCIN Input Noise HIN filter Deadtime & Shoot-Through
Figure 5
Prevent ion
Typical PCB circuit connected to
Input Noise LIN
the RFE pin
filter VDD Under- The Fault function allows the IPM to report a Fault COM voltage detection condition to the microncontroller by pulling the RFE pin low in one of two situations. The first is an under- voltage condition on VDD and the second is when the ITRIP ITRIP pin sees a voltage rising above V ITRIP IT,TH+. Noise filter The programmable fault clear timer function provides a means of automatically re-enabling the module operation a preset amount of time (TFLT-CLR) after the fault condition has disappeared. Figure 6 RFE Noise filter shows the RFE-related circuit block diagram inside the IPM. The length of TFLT-CLR can be determined by using the formula below. VRFE(t) = 3.3V * (1 – e-t/RC)
Figure 6 RFE internal circuit structure
TFLT-CLR = -RRCIN * CRCIN * ln(1-VIN,TH+/3.3V) For example, if RRCIN is 1.2MΩ and CRCIN is 1nF, the TFLT-
U/VS1, V/VS2, W/VS3 (High side emitter and low side
CLR is about 1.7ms with VIN,TH+ of 2.5V. It is also
collector)
important to note that CRCIN needs to be minimized in These pins are motor U, V, W input pins. order to make sure it is fully discharged in case of over current event.
V+ (Positive bus input voltage, Pin 23)
Since the ITRIP pin has a 500ns input filter, it is The high side IGBTs are connected to the bus appropriate to ensure that CRCIN will be discharged voltage. It is noted that the bus voltage should not below VIN,TH- by the open-drain MOSFET, after 350ns. exceed 450V. Therefore, the max CRCIN can be calculated as: Final Datashet 6 Revision 2.0 2019-02-11 Document Outline Description Features Potential Applications Product validation Table 1 Part Ordering Table Table of contents 1 Internal Electrical Schematic 2 Pin Configuration 3 Absolute Maximum Rating 4 Thermal Characteristics 5 Recommended Operating Conditions 6 Static Parameters 7 Dynamic Parameters 8 Thermistor Characteristics 9 Mechanical Characteristics and Ratings 10 Qualification Information 11 Diagrams & Tables 12 Application Guide 13 Package Outline 14 Revision History Disclaimer
Pin Configuration VRFE(t) = 3.3V * e-t/RC < VIN,TH- +3.3V CRCIN < 500ns / ( - ln (VIN,TH- / 3.3V) * RRFE_ON) Consider VIN,TH- of 0.8V and RRFE_ON of 50ohm, CRCIN RRCIN 6 L- should be less than 7nF. It is also suggested to use a 1 To Microcontroller 3 2 RRCIN of between 0.5MΩ and 2MΩ. 6 RFE IM CRCIN Input Noise HIN filter Deadtime & Shoot-Through
Figure 5
Prevent ion
Typical PCB circuit connected to
Input Noise LIN
the RFE pin
filter VDD Under- The Fault function allows the IPM to report a Fault COM voltage detection condition to the microncontroller by pulling the RFE pin low in one of two situations. The first is an under- voltage condition on VDD and the second is when the ITRIP ITRIP pin sees a voltage rising above V ITRIP IT,TH+. Noise filter The programmable fault clear timer function provides a means of automatically re-enabling the module operation a preset amount of time (TFLT-CLR) after the fault condition has disappeared. Figure 6 RFE Noise filter shows the RFE-related circuit block diagram inside the IPM. The length of TFLT-CLR can be determined by using the formula below. VRFE(t) = 3.3V * (1 – e-t/RC)
Figure 6 RFE internal circuit structure
TFLT-CLR = -RRCIN * CRCIN * ln(1-VIN,TH+/3.3V) For example, if RRCIN is 1.2MΩ and CRCIN is 1nF, the TFLT-
U/VS1, V/VS2, W/VS3 (High side emitter and low side
CLR is about 1.7ms with VIN,TH+ of 2.5V. It is also
collector)
important to note that CRCIN needs to be minimized in These pins are motor U, V, W input pins. order to make sure it is fully discharged in case of over current event.
V+ (Positive bus input voltage, Pin 23)
Since the ITRIP pin has a 500ns input filter, it is The high side IGBTs are connected to the bus appropriate to ensure that CRCIN will be discharged voltage. It is noted that the bus voltage should not below VIN,TH- by the open-drain MOSFET, after 350ns. exceed 450V. Therefore, the max CRCIN can be calculated as: Final Datashet 6 Revision 2.0 2019-02-11 Document Outline Description Features Potential Applications Product validation Table 1 Part Ordering Table Table of contents 1 Internal Electrical Schematic 2 Pin Configuration 3 Absolute Maximum Rating 4 Thermal Characteristics 5 Recommended Operating Conditions 6 Static Parameters 7 Dynamic Parameters 8 Thermistor Characteristics 9 Mechanical Characteristics and Ratings 10 Qualification Information 11 Diagrams & Tables 12 Application Guide 13 Package Outline 14 Revision History Disclaimer