Datasheet MA12040 (Infineon) - 5
| Fabricante | Infineon |
| Descripción | 2x40W ultra power efficient, fully Integrated audio amplifier IC with analog input |
| Páginas / Página | 86 / 5 — Table 4-1. Pin No. Name. Type1. Description. www.infineon.com |
| Revisión | 01_00 |
| Formato / tamaño de archivo | PDF / 1.7 Mb |
| Idioma del documento | Inglés |
Table 4-1. Pin No. Name. Type1. Description. www.infineon.com
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4.2 Pin Function
Table 4-1 Pin No. Name Type1 Description
1 PVSS P Power ground for internal power amplifiers 2 PVSS P Power ground for internal power amplifiers 3 CF0AN P Connect to external flying capacitor negative terminal for amplifier channel 0A
4 OUT0A O Audio power output 0A 5 OUT0A O Audio power output 0A 6 CF0AP P Connect to external flying capacitor positive terminal for amplifier channel 0A 7 PVDD P Power supply for internal power amplifiers 8 PVDD P Power supply for internal power amplifiers 9 CF0BP P Connect to external flying capacitor positive terminal for amplifier channel 0B 10 OUT0B O Audio power output 0B 11 OUT0B O Audio power output 0B 12 CF0BN P Connect to external flying capacitor negative terminal for amplifier channel 0B 13 PVSS P Power ground for internal power amplifiers 14 PVSS P Power ground for internal power amplifiers 15 /CLIP O Audio clipping indicator (open drain output), pulled low when clipping occurs 16 /ERROR O Error indicator (open drain output), pulled low when an error occurs 17 AVDD P Power supply for internal analog circuitry 18 CMSE O Decoupling pin for internally generated common-mode voltage in SE configuration. Should be externally decoupled to AVSS. 19 AVSS P Ground for internal analog circuitry 20 CREF O Decoupling pin for internally generated analog reference voltage. Should be externally decoupled to AVSS. 21 IN0A I Analog audio input 0A 22 IN0B I Analog audio input 0B 23 IN1A I Analog audio input 1A 24 IN1B I Analog audio input 1B 25 AVSS P Ground for internal analog circuitry 26 DVSS P Ground for internal digital circuitry 27 SCL IO I2C bus serial clock 28 AD0 I I2C device address select 0 (see “MCU/Serial control interface” section)
29 AD1 I I2C device address select 1 (see “MCU/Serial control interface” section) 30 SDA IO I2C bus serial data 31 CLKM/S I Clock master/slave mode select. When pulled low the device is in clock slave mode. When pulled high the device is in master mode. 32 CLKIO IO Clock input when in clock slave mode (CLKM/S is pulled low) or clock output when in master mode (CLKM/S is pulled high) 33 /ENABLE I When pulled high, the device is reset and kept in an inactive state with minimum power consumption. 34 /MUTE I Mute audio output when pulled low 35 PVSS P Power ground for internal power amplifiers 36 PVSS P Power ground for internal power amplifiers 37 CF1BN P Connect to external flying capacitor negative terminal for amplifier channel 1B 38 OUT1B O Audio power output 1B 39 OUT1B O Audio power output 1B Datasheet Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com
page 5 of 86 2018-07-17
Table 4-1 Pin No. Name Type1 Description
1 PVSS P Power ground for internal power amplifiers 2 PVSS P Power ground for internal power amplifiers 3 CF0AN P Connect to external flying capacitor negative terminal for amplifier channel 0A
4 OUT0A O Audio power output 0A 5 OUT0A O Audio power output 0A 6 CF0AP P Connect to external flying capacitor positive terminal for amplifier channel 0A 7 PVDD P Power supply for internal power amplifiers 8 PVDD P Power supply for internal power amplifiers 9 CF0BP P Connect to external flying capacitor positive terminal for amplifier channel 0B 10 OUT0B O Audio power output 0B 11 OUT0B O Audio power output 0B 12 CF0BN P Connect to external flying capacitor negative terminal for amplifier channel 0B 13 PVSS P Power ground for internal power amplifiers 14 PVSS P Power ground for internal power amplifiers 15 /CLIP O Audio clipping indicator (open drain output), pulled low when clipping occurs 16 /ERROR O Error indicator (open drain output), pulled low when an error occurs 17 AVDD P Power supply for internal analog circuitry 18 CMSE O Decoupling pin for internally generated common-mode voltage in SE configuration. Should be externally decoupled to AVSS. 19 AVSS P Ground for internal analog circuitry 20 CREF O Decoupling pin for internally generated analog reference voltage. Should be externally decoupled to AVSS. 21 IN0A I Analog audio input 0A 22 IN0B I Analog audio input 0B 23 IN1A I Analog audio input 1A 24 IN1B I Analog audio input 1B 25 AVSS P Ground for internal analog circuitry 26 DVSS P Ground for internal digital circuitry 27 SCL IO I2C bus serial clock 28 AD0 I I2C device address select 0 (see “MCU/Serial control interface” section)
29 AD1 I I2C device address select 1 (see “MCU/Serial control interface” section) 30 SDA IO I2C bus serial data 31 CLKM/S I Clock master/slave mode select. When pulled low the device is in clock slave mode. When pulled high the device is in master mode. 32 CLKIO IO Clock input when in clock slave mode (CLKM/S is pulled low) or clock output when in master mode (CLKM/S is pulled high) 33 /ENABLE I When pulled high, the device is reset and kept in an inactive state with minimum power consumption. 34 /MUTE I Mute audio output when pulled low 35 PVSS P Power ground for internal power amplifiers 36 PVSS P Power ground for internal power amplifiers 37 CF1BN P Connect to external flying capacitor negative terminal for amplifier channel 1B 38 OUT1B O Audio power output 1B 39 OUT1B O Audio power output 1B Datasheet Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com
page 5 of 86 2018-07-17