Datasheet 5L2503 (IDT) - 8

5L2503 Datasheet
Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause permanent damage to the device. Functional operation of the 5L2503 at absolute maximum ratings is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Table 13: Absolute Maximum Ratings Item Rating
Supply Voltage, VDD1_8, VDDOUTx 1.89V
Inputs
Other Inputs -0.5V to VDD1_8/VDDOUTx Outputs, VDDOUTx (LVCMOS) -0.5V to VDDOUTx + 0.5V Outputs, IO (SDA) 10mA Package Thermal Impedance, ΘJA 42°C/W (0 mps) Package Thermal Impedance, ΘJC 41.8°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C ESD Human Body Model 2000V Junction Temperature 125°C
Recommended Operating Conditions Table 14: Recommended Operating Conditions Symbol Parameter Minimum Typical Maximum Units
VDDOUTx Power supply voltage for supporting 1.8V output and all other 1.71 1.8 1.89 V outputs. VDD1_8 Power supply voltage for core logic functions. 1.71 1.8 1.89 V TA Operating temperature, ambient. -40 85 °C CLOAD_OUT Maximum load capacitance (1.8V LVCMOS only). 5 pF tPU Power up time for all VDDs to reach minimum specified voltage 0.05 3 ms (power ramps must be monotonic). ©2017 Integrated Device Technology, Inc. 8 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History