Datasheet RFP30N06LE, RF1S30N06LESM (Fairchild) - 5
| Fabricante | Fairchild |
| Descripción | 30A, 60V, ESD Rated, 0.047 Ohm, Logic Level N-Channel Power MOSFETs |
| Páginas / Página | 8 / 5 — RFP30N06LE, RF1S30N06LESM. Typical Performance Curves. (Continued). 2000. … |
| Formato / tamaño de archivo | PDF / 194 Kb |
| Idioma del documento | Inglés |
RFP30N06LE, RF1S30N06LESM. Typical Performance Curves. (Continued). 2000. ) V 60. 5.0. ( E. G A. VDD = BVDSS. ISS. 3.75. 1500
Línea de modelo para esta hoja de datos
Versión de texto del documento
RFP30N06LE, RF1S30N06LESM Typical Performance Curves
Unless Otherwise Specified
(Continued) 2000 ) V 60 5.0 ) ( V E ( E G A G VDD = BVDSS VDD = BVDSS A C T T ISS L L ) 3.75 1500 45 O F O p V V ( VGS = 0V, f = 1MHz URCE 30 2.5 URCE ANCE O 1000 CISS = CGS + CGD O 0.75 BV 0.75 BV S DSS DSS S CIT C O 0.50 BV 0.50 BV A RSS = CGD T DSS DSS O P C T OSS
≈
CDS + CGD 0.25 BV 0.25 BV DSS DSS E 15 1.25 T , CA COSS R A L = 2.0
Ω
C 500 I , DRAIN G(REF) = 0.62mA , G VGS = 5V GS C DS RSS V 0 0 V IG(REF) IG(REF) 0 20 t, TIME (s) 80 0 5 10 15 20 25 IG(ACT) IG(ACT) VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L tP VDS VARY tP TO OBTAIN IAS + V REQUIRED PEAK I R DD AS G VDD VGS - DUT tP 0V IAS 0 0.01
Ω
tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) R t t L r f VDS VDS 90% 90% V + GS VGS - 10% 10% 0 0V 90% R DUT GS VGS 50% 50% PULSE WIDTH 10% 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
©2004 Fairchild Semiconductor Corporation RFP30N06LE, RF1S30N06LESM Rev. B1
Unless Otherwise Specified
(Continued) 2000 ) V 60 5.0 ) ( V E ( E G A G VDD = BVDSS VDD = BVDSS A C T T ISS L L ) 3.75 1500 45 O F O p V V ( VGS = 0V, f = 1MHz URCE 30 2.5 URCE ANCE O 1000 CISS = CGS + CGD O 0.75 BV 0.75 BV S DSS DSS S CIT C O 0.50 BV 0.50 BV A RSS = CGD T DSS DSS O P C T OSS
≈
CDS + CGD 0.25 BV 0.25 BV DSS DSS E 15 1.25 T , CA COSS R A L = 2.0
Ω
C 500 I , DRAIN G(REF) = 0.62mA , G VGS = 5V GS C DS RSS V 0 0 V IG(REF) IG(REF) 0 20 t, TIME (s) 80 0 5 10 15 20 25 IG(ACT) IG(ACT) VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms VDS BVDSS L tP VDS VARY tP TO OBTAIN IAS + V REQUIRED PEAK I R DD AS G VDD VGS - DUT tP 0V IAS 0 0.01
Ω
tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) R t t L r f VDS VDS 90% 90% V + GS VGS - 10% 10% 0 0V 90% R DUT GS VGS 50% 50% PULSE WIDTH 10% 0 FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
©2004 Fairchild Semiconductor Corporation RFP30N06LE, RF1S30N06LESM Rev. B1