Product Brief PIC16(L)F184XX (Microchip) - 10

FabricanteMicrochip
DescripciónFull-Featured, Low Pin Count Microcontrollers with XLP
Páginas / Página18 / 10 — PIC16(L)F184XX. I/O. ADC. NCO. DAC. DSM. imers. CCP. CLC. PWM. CWG. MSSP. …
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Idioma del documentoInglés

PIC16(L)F184XX. I/O. ADC. NCO. DAC. DSM. imers. CCP. CLC. PWM. CWG. MSSP. ZCD. CLKR. Pull-up. Basic. Reference. EUSART. Interrupts. 16-pin UQFN. Comparator

PIC16(L)F184XX I/O ADC NCO DAC DSM imers CCP CLC PWM CWG MSSP ZCD CLKR Pull-up Basic Reference EUSART Interrupts 16-pin UQFN Comparator

Versión de texto del documento

PIC16(L)F184XX I/O ADC NCO DAC DSM imers CCP CLC T PWM CWG MSSP ZCD CLKR Pull-up Basic Reference EUSART Interrupts 16-pin UQFN Comparator 14-pin PDIP/SOIC/TSSOP
CWG1B SCK1 — — ADCGRDB — C2OUT — — — — CCP2OUT PWM7OUT — CK1
(3)
CLC2OUT — — — — CWG2B SCK2 CWG1C SCL1
(3)
— — — — — — — — — CCP3OUT — — TX1 CLC3OUT — — — — CWG2C SCL2
(3)
CWG1D SDA1
(3)
— — — — — — — — — CCP4OUT — — — CLC4OUT — — — — CWG2D SDA2
(3) Note: 
1. This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. 2. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. 3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. 4. These pins are configured for I2C logic levels. PPS assignments to the other pins will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. 5. MSSP2 is not available on the PIC16(L)F18424 or PIC16(L)F18444 devices.
2 20-Pin Allocation Table I/O ADC NCO DAC DSM imers CCP CLC T PWM CWG MSSP ZCD CLKR Pull-up Basic Reference EUSART Interrupts 20-pin UQFN Comparator 20-pin PDIP/SOIC/TSSOP
ICDDAT/ RA0 19 16 ANA0 — C1IN0+ — DAC1OUT1 — — — — — — — — — — IOCA0 Y ICSPDAT C1IN0- ICDCLK/ ADCVREF DAC1VREF RA1 18 15 ANA1 — MDSRC
(1)
— — — — SS2
(1)
— — — — IOCA1 Y + + C2IN0- ICSPCLK CWG1IN
(1)
RA2 17 14 ANA2 ADCVREF- — — DAC1VREF- — T0CKI
(1)
— — — ZCD1 — CLCIN0
(1)
— IOCA2 Y INT0
(1)
CWG2IN
(1)
MCLR RA3 4 1 — — — — — — — — — — — — — — — IOCA3 Y VPP RA4 3 20 ANA4 — — — — — T1G
(1)
CCP4IN
(1)
— — — — — — — IOCA4 Y CLKOUT © 2017 Microchip Technology Inc.
Product Brief
DS40001894B-page 10 Document Outline Description Core Features Memory Operating Characteristics Power-Saving Operation Modes eXtreme Low-Power (XLP) Features Digital Peripherals Analog Peripherals Flexible Oscillator Structure Family Types Packages Pin Diagrams 1. 14/16-Pin Diagrams 2. 20-Pin Diagrams 3. 28-Pin Diagrams Pin Allocation Tables 1. 14/16-Pin Allocation Table 2. 20-Pin Allocation Table 3. 28-Pin Allocation Table The Microchip Web Site Customer Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service