Product Brief PIC18 Q43 (Microchip) - 7
| Fabricante | Microchip |
| Descripción | PIC18 Q43 combines our most popular, versatile and easy to use Core Independent Peripherals with advanced interconnection capabilities that make sophisticated hardware customization effortless |
| Páginas / Página | 20 / 7 — PIC18 Q43. Figure 2. 28-pin , VQFN. Note: . Figure 3. 40-pin PDIP. … |
| Formato / tamaño de archivo | PDF / 273 Kb |
| Idioma del documento | Inglés |
PIC18 Q43. Figure 2. 28-pin , VQFN. Note: . Figure 3. 40-pin PDIP. Product Brief
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PIC18 Q43 Figure 2. 28-pin , VQFN
P Rev. 00-000028B P T K 6/23/2017 L /V R DA C L P P C S /M /ICS /IC 1 0 3 7 6 5 4 A A E B B B B R R R R R R R 28 27 26 25 24 23 22 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 RA5 4 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 C C C C C C C R R R R R R R Filename: 00-000040A.vsd Title: 40-pin DIP Last Edit: 10/3/2018 First Used: N/A
Note:
It is recommended that the exposed bottom pad be connected to V Notes: Generic 40-pin dual in-line diagram SS, however it must not be the only VSS connection to the device.
Figure 3. 40-pin PDIP
Rev. 00-000040A 10/3/2018 MCLR/VPP/RE3 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 33 RB0 RE1 9 32 VDD RE2 10 31 VSS VDD 11 30 RD7 VSS 12 29 RD6 RA7 13 28 RD5 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 RC2 17 24 RC5 RC3 18 23 RC4 RD0 19 22 RD3 RD1 20 21 RD2 © 2019 Microchip Technology Inc.
Product Brief
DS40002069B-page 7 Document Outline Description PIC18 Q43 Family Types Core Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Packages Pin Diagrams Pin Allocation Tables Table of Contents The Microchip Web Site Customer Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service
P Rev. 00-000028B P T K 6/23/2017 L /V R DA C L P P C S /M /ICS /IC 1 0 3 7 6 5 4 A A E B B B B R R R R R R R 28 27 26 25 24 23 22 RA2 1 21 RB3 RA3 2 20 RB2 RA4 3 19 RB1 RA5 4 18 RB0 VSS 5 17 VDD RA7 6 16 VSS RA6 7 15 RC7 8 9 10 11 12 13 14 0 1 2 3 4 5 6 C C C C C C C R R R R R R R Filename: 00-000040A.vsd Title: 40-pin DIP Last Edit: 10/3/2018 First Used: N/A
Note:
It is recommended that the exposed bottom pad be connected to V Notes: Generic 40-pin dual in-line diagram SS, however it must not be the only VSS connection to the device.
Figure 3. 40-pin PDIP
Rev. 00-000040A 10/3/2018 MCLR/VPP/RE3 1 40 RB7/ICSPDAT RA0 2 39 RB6/ICSPCLK RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4 6 35 RB2 RA5 7 34 RB1 RE0 8 33 RB0 RE1 9 32 VDD RE2 10 31 VSS VDD 11 30 RD7 VSS 12 29 RD6 RA7 13 28 RD5 RA6 14 27 RD4 RC0 15 26 RC7 RC1 16 25 RC6 RC2 17 24 RC5 RC3 18 23 RC4 RD0 19 22 RD3 RD1 20 21 RD2 © 2019 Microchip Technology Inc.
Product Brief
DS40002069B-page 7 Document Outline Description PIC18 Q43 Family Types Core Features Memory Operating Characteristics Power-Saving Functionality Digital Peripherals Analog Peripherals Clocking Structure Programming/Debug Features Packages Pin Diagrams Pin Allocation Tables Table of Contents The Microchip Web Site Customer Change Notification Service Customer Support Microchip Devices Code Protection Feature Legal Notice Trademarks Quality Management System Certified by DNV Worldwide Sales and Service