Datasheet GW1NRF (GOWIN Semiconductor) - 20

link to page 55 link to page 55 link to page 62 link to page 62 link to page 55 link to page 55 link to page 60 link to page 60 link to page 60 link to page 61 link to page 61 3Architecture 3.2SoC System resource for user designs with the clock precision reaching ±5%. See 3.8Clock, 3.12On Chip Oscillator for more detailed information. FPGA provides abundant CRUs, connecting all the resources in the FPGA. For example, routing resources distributed in CFU and IOB connect resources in CFU and IOB. Routing resources can automatically be generated by Gowin software. In addition, the GW1NRF series of Bluetooth FPGA products also provide abundant GCLKs, long wires (LW), global set/reset (GSR), and programming options, etc. See 3.8Clock, 3.9Long Wire (LW), 3.10Global Set/Reset (GSR) for more detailed information.
3.2 SoC System
The CPU is a 32-bit ARC EM4 V3.2 by Synopsys, with an integrated floating point unit (FPU), which is optimized for area, power, and performance efficiency. The ARC’s RISC pipe-lined architecture with mostly single-cycle operations is approximately 30% more efficient than other popular 32-bit CPUs. Effective use of the sleep instruction minimizes power consumption. During sleep mode the entire MCU subsystem can be shut off and only the power management system and required state retention memories (if any) need to be powered. The power management system will properly wakeup the MCU subsystem when it is needed. The CPU is awakened on an interrupt, quickly executes the required functions with a 24MHz clock, and returns to sleep. A hardware interrupt handler is implemented with several interrupt levels in order to define high and low priority functions. There are four additional CPU coprocessors: 1) an AES-128 crypto engine, 2) LOG2, 3) JLI_Rebase, and 4) a CRC calculator. Dedicated CPU instructions are defined to run AES encryption/decryption, calculate a log2() function, a function to help with rebasing the JLI table, and a function to calculate CRC values respectively.
FPU
The ARC also includes a Floating Point Unit (FPU) compliant with the IEEE 754-2008. FPU supports for all IEEE specified rounding modes The FPU has single precision hardware support for multiply, add, subtract, integer/float conversions, compare, divide, and square root. All FPU operations are supported by the Metaware compiler for ARC EM4
Memories
Code memory is split to ROM, RAM and OTP and use is optimized for power consumption. In sleep mode ROM can be shut off without losing its contents while RAM will lose its contents and needs to be reloaded. Therefore all critical functions for Bluetooth low energy controller and hostare implemented in the ROM. 48kB RAM is available for application and patch development. These can then be moved into OTP for production. The patching system is based on using instruction index tables and dedicated CPU instructions. All functions that are to be patched must use index table call. The index table is loaded from ROM into RAM and rebuilt during the boot process. DS891-1.0E 11(76) Document Outline Disclaimer Revision History Contents List of Figures List of Tables 1 About This Guide 1.1 Purpose 1.2 Supported Products 1.3 Related Documents 1.4 Abbreviations and Terminology 1.5 Support and Feedback 2 General Description 2.1 Features 2.2 Product Resources 2.3 Package Information 3 Architecture 3.1 Architecture Overview 3.2 SoC System FPU Memories Security Peripherals 3.2.1 Bluetooth Module Bluetooth Controller Mode Bluetooth Companion Mode Bluetooth Application Mode 3.2.2 Timers 3.2.3 Power Management DC DC Switching Power Supply Supply Monitoring 3.2.4 RF Description 3.2.5 Operating Modes 3.2.6 Software Development 3.3 Configurable Function Unit 3.3.1 CLU Register 3.3.2 CRU 3.4 IOB 3.4.1 I/O Buffer 3.4.2 True LVDS Design 3.4.3 I/O Logic IODELAY I/O Register IEM De-serializer DES and Clock Domain Transfer Serializer SER 3.4.4 I/O Logic Modes Basic Mode SDR Mode Generic DDR Mode IDES4 OSER4 Mode IVideo Mode OVideo Mode IDES8 Mode OSER8 Mode IDES10 Mode OSER10 Mode 3.5 Block SRAM (B-SRAM) 3.5.1 Introduction 3.5.2 Configuration Mode 3.5.3 Mixed Data Bus Width Configuration 3.5.4 Byte-enable 3.5.5 Parity Bit 3.5.6 Synchronous operation 3.5.7 Power up Conditions 3.5.8 Operation Modes Single Port Mode Dual Port Mode Semi-Dual Port Mode Read Only 3.5.9 B-SRAM Operation Modes Read Mode Pipeline Mode Bypass Mode Write Mode 3.5.10 Clock Operations Independent Clock Mode Read/Write Clock Operation Single Port Clock Mode 3.6 User Flash 3.6.1 Introduction 3.6.2 User Flash Ports 3.6.3 User Flash Mode Truth Table User Modes 3.7 DSP 3.7.1 Introduction Macro PADD MULT ALU 3.7.2 DSP Operations 3.8 Clock 3.8.1 Global Clock 3.8.2 PLL 3.8.3 HCLK 3.8.4 DLL 3.9 Long Wire (LW) 3.10 Global Set/Reset (GSR) 3.11 Programming Configuration 3.11.1 SRAM Configuration 3.11.2 Flash Configuration 3.12 On Chip Oscillator 4 AC/DC Characteristics 4.1 Operating Conditions 4.2 ESD 4.3 DC Characteristics 4.3.1 Static Current 4.3.2 RF Parameters 4.3.3 I/O Characteristics 4.4 Switching Characteristics 4.4.1 Internal Switching Characteristics 4.4.2 External Switching Characteristics 4.5 User Flash Characteristics 4.5.1 DC Characteristics1 4.5.2 Timing Parameters1,5,6 4.5.3 Operation Timing Diagrams 4.6 Configuration Interface Timing Specification 4.6.1 JTAG Port Timing Specifications 4.6.2 AUTO BOOT Port Timing Specifications 4.6.3 SSPI Port Timing Specifications 4.6.4 MSPI Port Timing Specifications 4.6.5 DUAL BOOT 4.6.6 CPU 4.6.7 SERIAL 5 Ordering Information 5.1 Part Name 5.2 Package Mark