Datasheet TLS715B0NAV50 (Infineon) - 8
| Fabricante | Infineon |
| Descripción | OPTIREG Linear TLS715B0NAV50. Low dropout li near voltage regulator |
| Páginas / Página | 22 / 8 — OPTIREG™ Linear TLS715B0NAV50 Low dropout linear voltage regulator … |
| Revisión | 01_10 |
| Formato / tamaño de archivo | PDF / 686 Kb |
| Idioma del documento | Inglés |
OPTIREG™ Linear TLS715B0NAV50 Low dropout linear voltage regulator General product characteristics. 3.3. Thermal resistance
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OPTIREG™ Linear TLS715B0NAV50 Low dropout linear voltage regulator General product characteristics 3.3 Thermal resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to
www.jedec.org
.
Table 3 Thermal resistance Parameter Symbol Values Unit Note or Number Test Condition Min. Typ. Max. Package version PG-TSNP-7
Junction to case1) RthJC – 14 – K/W – P_4.3.1 Junction to ambient RthJA – 61 – K/W 2s2p board2) P_4.3.2 Junction to ambient RthJA – 196 – K/W 1s0p board, footprint P_4.3.3 only3) Junction to ambient RthJA – 94 – K/W 1s0p board, 300 mm2 P_4.3.4 heatsink area on PCB3) Junction to ambient RthJA – 83 – K/W 1s0p board, 600 mm2 P_4.3.5 heatsink area on PCB3) 1) Not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 × 70 µm Cu). Datasheet 8 Rev. 1.1 2019-07-31 Document Outline Features Potential applications Product validation Description Table of contents 1 Block diagram 2 Pin configuration 2.1 Pin assignment PG-TSNP-7 2.2 Pin definitions and functions PG-TSNP-7 3 General product characteristics 3.1 Absolute maximum ratings 3.2 Functional range 3.3 Thermal resistance 4 Block description and electrical characteristics 4.1 Voltage regulation 4.2 Typical performance characteristics voltage regulator 4.3 Current consumption 4.4 Typical performance characteristics current consumption 4.5 Enable 4.6 Typical performance characteristics enable 5 Application information 5.1 Application diagram 5.2 Selection of external components 5.2.1 Input pin 5.2.2 Output pin 5.3 Thermal considerations 5.4 Reverse polarity protection 5.5 Further application information 6 Package information 7 Revision history
OPTIREG™ Linear TLS715B0NAV50 Low dropout linear voltage regulator General product characteristics 3.3 Thermal resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to
www.jedec.org
.
Table 3 Thermal resistance Parameter Symbol Values Unit Note or Number Test Condition Min. Typ. Max. Package version PG-TSNP-7
Junction to case1) RthJC – 14 – K/W – P_4.3.1 Junction to ambient RthJA – 61 – K/W 2s2p board2) P_4.3.2 Junction to ambient RthJA – 196 – K/W 1s0p board, footprint P_4.3.3 only3) Junction to ambient RthJA – 94 – K/W 1s0p board, 300 mm2 P_4.3.4 heatsink area on PCB3) Junction to ambient RthJA – 83 – K/W 1s0p board, 600 mm2 P_4.3.5 heatsink area on PCB3) 1) Not subject to production test, specified by design 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product (Chip + Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 × 70 µm Cu). Datasheet 8 Rev. 1.1 2019-07-31 Document Outline Features Potential applications Product validation Description Table of contents 1 Block diagram 2 Pin configuration 2.1 Pin assignment PG-TSNP-7 2.2 Pin definitions and functions PG-TSNP-7 3 General product characteristics 3.1 Absolute maximum ratings 3.2 Functional range 3.3 Thermal resistance 4 Block description and electrical characteristics 4.1 Voltage regulation 4.2 Typical performance characteristics voltage regulator 4.3 Current consumption 4.4 Typical performance characteristics current consumption 4.5 Enable 4.6 Typical performance characteristics enable 5 Application information 5.1 Application diagram 5.2 Selection of external components 5.2.1 Input pin 5.2.2 Output pin 5.3 Thermal considerations 5.4 Reverse polarity protection 5.5 Further application information 6 Package information 7 Revision history