Datasheet APR348 (Diodes) - 6

APR348 Synchronous Rectification Principle Description
(continued)
The Value and Meaning of Rx Resistance
On DCM operation after the secondary rectifier stops conduction, the primary MOSFET drain-to-source generates a ringing waveform, which results from the resonant of primary inductance and equivalent switch-device output capacitance. This ringing waveform most likely leads to the synchronous rectifier fault conduction. Therefore, along with an internal fixed volt-sec setting, the APR348 can also use a drain-to-source voltage slew rate detection to determine whether synchronous rectification MOSFET can turn on. The APR348 senses the voltage of VDET pin. The device generates a programmable tSLOPE by usage of the Rx pin resistor and an internal sink current. This time calculation starts from VDET = 2V,

VDET is compared with VTHON within the tSLOPE time. If VDET < VTHON, the IC outputs a positive drive voltage after a turn-on delay time (tDON). Slew-
T
rate time, tSLOPE, can be programmed with the following equation. The Rx is the resistance connected on the Rx pin.
C U D
t = 110𝑛𝑠 × Rx SLOPE 300𝐾𝛺
O R
If the Rx pin floats, an internal timer is used to set a fixed tSLOPE 120ns for slew rate calculation.
P W Synchronous Rectification Forward Regulation and Turn-Off Stage E
Once the synchronous rectification gate outputs high levels and the synchronous rectification MOSFET turns on, the secondary-side current goes
N
through synchronous rectification MOSFET. The voltage drop on synchronous rectification MOSFET is found by RDS(ON) × secondary-side current. After minimum turn-on time tONMIN, the IC continuously monitors VDS by the VDET pin and generates a pull-down current from the MOSFET gate until VDET > -45mV. The MOSFET drain-to-source voltage would remain at around -45mV with the secondary-side current decreasing. Real MOSFET gate voltage depends on the MOSFET characteristics and drain current. When the primary MOSFET turns on, the secondary VDS would rise up. Once VDET rises to trigger the turn-off threshold, the gate signal will be pulled down to GND. The synchronous rectification MOSFET gate voltage drops quickly from a low voltage to zero after a very short turn-off delay.
Light Load Mode (LL Mode)
The APR348 provides light-load mode at light or no load when the system goes into burst or no-load mode with interval-time pulse for low standby loss. The IC internal has two timers to record 640µs and 2.5ms. When the interval-time is between 640µs and 10ms, the gate drive outputs with skipping the first two cycles. When the interval time is over 2.5ms, gate drive outputs with skipping the first eight cycles.
VDD Regulator and UVLO Protection
The VDD is an internal linear regulator output. The capacitor at VDD pin is charged from VDET or VCC side. When the synchronous rectification MOSFET and the IC are connected in low side, the VDD is supplied by both VDET pin and VCC pin. When synchronous rectification MOSFET and IC are connected in high side, the VDD is supplied only via VDET. A large capacitance at VDD pin is proposed for system design. The APR348 also has the UVLO protection. When VDD drops below VDD_UVLO, the IC will stop working. APR348 6 of 9 December 2019 Document number: DS42016 Rev. 3 - 2
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