Datasheet LTM8024 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | 40VIN, Dual 3.5A or Single 7A Silent Switcher μModule Regulator |
| Páginas / Página | 24 / 10 — PIN FUNCTIONS. PG1/PG2 (Pins L3, K3):. SYNC (Pin L4):. TEST (Pin L2):. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 2.8 Mb |
| Idioma del documento | Inglés |
PIN FUNCTIONS. PG1/PG2 (Pins L3, K3):. SYNC (Pin L4):. TEST (Pin L2):. BLOCK DIAGRAM
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LTM8024
PIN FUNCTIONS PG1/PG2 (Pins L3, K3):
The PGn pin is the open-drain
SYNC (Pin L4):
External Clock Synchronization Input. output of an internal comparator. PGn remains low until Ground this pin for low ripple Burst Mode operation at the FB1 pin is within ±7.5% of the final regulation voltage, low output loads; this will also disable the CLKOUT func- and there are no fault conditions. PGn is pulled low during tion. Apply a DC voltage between 2.8V and 4.0V for spread VIN1 UVLO, VCC UVLO, thermal shutdown, or when RUN1 spectrum modulation. Float the SYNC pin for forced con- or RUN2 are low. tinuous operation without spread spectrum modulation.
TEST (Pin L2):
This pin is used in LTM8024 Apply a clock source to the SYNC pin for synchronization production testing. to an external frequency. The LTM8024 will be in forced continuous mode when an external frequency is applied.
BLOCK DIAGRAM
VIN1 BIAS HOUSEKEEPING AUX1 0.2µF CIRCUITRY 1.5µH RUN1 CURRENT VOUT1 MODE CONTROLLER TRSS1 249k 10pF 0.1µF FB1 SYNC UVLO PG1 RT VIN2 TEST CLKOUT 0.2µF CURRENT 1.5µH RUN2 VOUT2 MODE CONTROLLER TRSS2 AUX2 249k 10pF 0.1µF PG2 FB2 SHARE1 GND SHARE2 8024 BD Rev. A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package PHOTOGRAPH Revision History Typical Application Related Parts
PIN FUNCTIONS PG1/PG2 (Pins L3, K3):
The PGn pin is the open-drain
SYNC (Pin L4):
External Clock Synchronization Input. output of an internal comparator. PGn remains low until Ground this pin for low ripple Burst Mode operation at the FB1 pin is within ±7.5% of the final regulation voltage, low output loads; this will also disable the CLKOUT func- and there are no fault conditions. PGn is pulled low during tion. Apply a DC voltage between 2.8V and 4.0V for spread VIN1 UVLO, VCC UVLO, thermal shutdown, or when RUN1 spectrum modulation. Float the SYNC pin for forced con- or RUN2 are low. tinuous operation without spread spectrum modulation.
TEST (Pin L2):
This pin is used in LTM8024 Apply a clock source to the SYNC pin for synchronization production testing. to an external frequency. The LTM8024 will be in forced continuous mode when an external frequency is applied.
BLOCK DIAGRAM
VIN1 BIAS HOUSEKEEPING AUX1 0.2µF CIRCUITRY 1.5µH RUN1 CURRENT VOUT1 MODE CONTROLLER TRSS1 249k 10pF 0.1µF FB1 SYNC UVLO PG1 RT VIN2 TEST CLKOUT 0.2µF CURRENT 1.5µH RUN2 VOUT2 MODE CONTROLLER TRSS2 AUX2 249k 10pF 0.1µF PG2 FB2 SHARE1 GND SHARE2 8024 BD Rev. A 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Package PHOTOGRAPH Revision History Typical Application Related Parts