Datasheet 8V97003 (IDT) - 59

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Recommendations for Unused Input and Output Pins Inputs LVCMOS Control Pins
All control pins have internal pul up and pul down resistors; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
Outputs Output Pins
For any unused output, it can be left floating and disabled.
Schematic Example
Figure 25 shows a general application schematic example for the 8V97003. For power rails, bypass capacitors must be provided to all power supply pins. At least one bypass capacitor per power pin is suggested. Value can range from 0.01µF or 0.1µF. Mix values of bypass capacitors can help filtering wider range of power supply noise. The 8V97003 input is high impedance. The input termination depends on the termination requirement from the driver. There are two input termination examples in the schematic shown in Figure 25; both are designed for transmission line with characteristic impedance Zo = 50Ω. The first example, labeled “Input Reference” at the lower right corner of the schematic, shows an input termination scheme for accepting a reference clock from bench signal generators. 50Ω resistors, R82 and R83 to GND, present matched loads to signal generator’s source impedance; the reference clock signal is then AC-coupled with capacitors C156 and C157 to ensure proper DC-biased to level of VDDx/2 by voltage divider networks of R90, R91, R92, and R93. The second example shows an input termination scheme for accepting a reference clock from a TCXO. The values of R96, R96, R85, and R88 in this example are designed for a TCXO with a single-ended CMOS output on pin 5. They can be changed for different TCXO output signal types. The 8V97003 output pull-up loading can be resistors or inductors. For inductor pull-up loading, the inductor value is frequency dependent. One inductor value cannot cover all the output frequency range. For example, an inductance of L = 1.3nH that is suitable for approximately 6GHz operating frequency. The output can also drive single ended LO input. Figure 25 also shows an example of the 8V97003 output driving single-ended LO input of the mixer through an LC balun. The LC balun component values are frequency dependent. These values can be adjusted to optimize the performance. A single-ended LO receiver input also can tap to one side of the differential driver using resistor loading or inductor loading. For single-ended LO input, both sides of the differential driver still need to be loaded with a pull up. The output power level can also be adjusted further through programming. The loop filter values can be calculated to meet the loop bandwidth requirement (for detailed calculations, see Loop Filter Calculations). ©2020 Renesas Electronics Corporation 59 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History