Datasheet ADAR1000 (Analog Devices) - 4

FabricanteAnalog Devices
Descripción8 GHz to 16 GHz, 4-Channel, X Band and Ku Band Beamformer
Páginas / Página65 / 4 — ADAR1000. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. …
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ADAR1000. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit

ADAR1000 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit

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ADAR1000 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
Output Return Loss TX1, TX2, TX3, or TX4 pin −10 dB Input Return Loss RF_IO pin −12 dB Output Third-Order Intercept (IP3) Maximum gain setting, 1 MHz carrier spacing Nominal Bias Setting 9.5 GHz 20 dBm 11.5 GHz 21 dBm 14 GHz 22 dBm Low Bias Setting 9.5 GHz 15 dBm 11.5 GHz 16 dBm 14 GHz 16 dBm RECEIVE SECTION Maximum Measured Gain2 9.5 GHz Nominal bias setting 10 dB 11.5 GHz 9 dB 14 GHz 7 dB Maximum Channel Gain3 9.5 GHz Nominal bias setting 16 dB 11.5 GHz 15 dB 14 GHz 13 dB Gain Flatness Across any 1 GHz bandwidth From 9 GHz to 14 GHz ±1.0 dB From 8 GHz to 15 GHz ±1.7 dB Gain Variation vs. Temperature 11.5 GHz ±3 dB Input P1dB Nominal Bias Setting 9.5 GHz −16 dBm 11.5 GHz −16 dBm 14 GHz −15 dBm Low Bias Setting 9.5 GHz −13 dBm 11.5 GHz −12 dBm 14 GHz −10 dBm Input IP3 Maximum gain setting, carrier spacing 1 MHz Nominal Bias Setting 9.5 GHz −7 dBm 11.5 GHz −7 dBm 14 GHz −6 dBm Low Bias Setting 9.5 GHz −7 dBm 11.5 GHz −6 dBm 14 GHz −5 dBm Gain Adjustment Range Variable gain amplifier (VGA) and step ≥31 dB attenuator Gain Resolution ≤0.5 dB RMS Gain Error 0.2 dB Phase Adjustment Range 360 Degrees Phase Resolution 2.8 Degrees RMS Phase Error 2 Degrees Rev. A | Page 4 of 65 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Timing Diagrams SPI Block Write Mode SPI Write All Mode Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation RF Path Phase and Gain Control Power Detectors External Amplifier Bias DACs External Switch Control Transmit and Receive Control RF Subcircuit Bias Control and Enables ADC Operation Chip Addressing Memory Access Calibration Applications Information Gain Control Registers Switched Attenuator Control Phase Control Registers Transmit and Receive Subcircuit Control TR_SOURCE = 1 (TR Pin Control) TR_SOURCE = 0 (SPI Control) Transmit and Receive Switch Driver Control PA Bias Output Control LNA Bias Output Control Transmit/Receive Delay Control Transmit and Receive Mode Switching SPI Programming Example Powering the ADAR1000 Register Map Register Descriptions Outline Dimensions Ordering Guide