Datasheet SZ8463ML, SZ8463RL, SZ8463FML, SZ8463FML (Microchip) - 10

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KSZ8463ML/RL/FML/FRL TABLE 2-1: SIGNALS FOR KSZ8463ML/RL/FML/FRL Type Pin Pin Name (Note Description Number 2-1 )
1 RXM1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential). 2 RXP1 I/O Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential). 3 AGND GND Analog Ground. 4 TXM1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential). 5 TXP1 I/O Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential). 6 VDD_AL P This pin is used as an input for the low-voltage analog power. Its source should have appropriate filtering with a ferrite bead and capacitors. Set physical transmits output current. 7 ISET O Pull-down this pin with a 6.49 kΩ (1%) resistor to ground. 8 AGND GND Analog Ground. 9 VDD_A3.3 P 3.3V analog VDD input power supply (Must be well decoupled). 10 RXM2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (– differential). 11 RXP2 I/O Port 2 physical receive (MDI) or transmit (MDIX) signal (+ differential). 12 AGND GND Analog Ground. 13 TXM2 I/O Port 2 physical transmit (MDI) or receive (MDIX) signal (– differential). 14 TXP2 I/O Port 2 physical transmit (MDI) or receive (MDIX) signal (+ differential). Fiber signal detect input for port 2 in 100BASE-FX fiber mode. When in cop- 15 FXSD2 I per mode, this input is unused and should be pulled to GND. Note: This functionality is available only on the KSZ8463FML/FRL devices. This pin is used as a second input for the low-voltage analog power. Its 16 VDD_COL P source should have appropriate filtering with a ferrite bead and capacitors.
Full-Chip Power-Down
Active-Low (Low = Power-down; High or floating = Normal operation). While this pin is asserted low, all I/O pins will be tri-stated. All registers will be 17 PWRDN IPU set to their default state. While this pin is asserted, power consumption will be minimal. When the pin is de-asserted, power consumption will climb to nomi- nal and the device will be in the same state as having been reset by the reset pin (RSTN, pin 63). 18 X1 I
25 MHz Crystal or Oscillator Clock Connection
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to a VDD_IO voltage tolerant oscillator and X2 is a no connect. This clock require- ment is ±50 ppm. The KSZ8463RL has the option to use REFCLK_I (50 MHz) as its primary 19 X2 O clock input instead of X1 and X2. This is determined by the state of pin 41 (SPI_DO) at power-up/reset time. See Table 2-2 for details. (Applies to the KSZ8463RL/FRL devices only) 20 DGND GND Digital ground. 3.3V, 2.5V, or 1.8V digital V 21 VDD_IO P DD input power pin for IO logic and the internal low-voltage regulator. DS00002642A-page 10

 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical (PHY) Block 3.2 Media Access Controller (MAC) Block 3.3 Switch Block 3.4 IEEE 1588 Precision Time Protocol (PTP) Block 3.5 General Purpose and IEEE 1588 Input/Output (GPIO) 3.6 Using the GPIO Pins with the Trigger Output Units 3.7 Using the GPIO Pins with the Time Stamp Input Units 3.8 Device Clocks 3.9 Power 3.10 Power Management 3.11 Interrupt Generation on Power Management-Related Events 3.12 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 MII Management (MIIM) Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 MII Transmit Timing in MAC Mode 7.2 MII Receive Timing in MAC Mode 7.3 MII Receive Timing in PHY Mode 7.4 MII Transmit Timing in PHY Mode 7.5 Reduced MII (RMII) Timing 7.6 MIIM (MDC/MDIO) Timing 7.7 SPI Input and Output Timing 7.8 Auto-Negotiation Timing 7.9 Trigger Output Unit and Time Stamp Input Unit Timing 7.10 Reset and Power Sequence Timing 7.11 Reset Circuit 8.0 Reference Clock: Connection and Selection 9.0 Selection of Isolation Transformers 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service