Datasheet ADP1032 (Analog Devices) - 10

FabricanteAnalog Devices
DescripciónTwo-Channel, Isolated Micropower Management Unit with Seven Digital Isolators
Páginas / Página37 / 10 — ADP1032. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. MVD. MI …
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ADP1032. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. MVD. MI 1. 30 VINP. MSS 2. 29 SWP. MGND 3. EPGNDM. EPGNDP. 28 PGNDP. TOP VIEW

ADP1032 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS MVD MI 1 30 VINP MSS 2 29 SWP MGND 3 EPGNDM EPGNDP 28 PGNDP TOP VIEW

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ADP1032 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 D 2 1 D P PO PI PI RG ND EW CK W G ND MO M MVD MG MG MG P M G SL EN 41 40 39 38 37 36 35 34 33 32 31 MI 1 30 VINP M FP MSS 2 29 SWP MGND 3 EPGNDM EPGNDP 28 PGNDP ADP1032 TOP VIEW SGND2 4 27 SGND2 (Not to Scale) SGND1 5 26 DNC SSS 6 25 DNC EPGND2 S SO 7 24 DNC 8 9 1 10 1 12 13 14 15 16 17 18 19 20 21 22 23 SI C 2 3 2 1 CK T2 T1 B1 PI S DD1 DNC DNC DNC ND2 SW F DD2 PO PO V SYN OU G OU V S V SG S V S SG SG NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. EPGNDP IS INTERNALLY CONNECTED TO PGNDP,
003
EPGNDM IS INTERNALLY CONNECTED TO MGND, AND EPGND2 IS INTERNALLY CONNECTED TO SGND.
20363- Figure 3. Pin Configuration
Table 10. Pin Function Descriptions Isolation Pin No. Mnemonic Domain Direction Description
1 MI Master Output SPI Data Output from the Slave MI and SO Line. This pin is paired with SO. On the slave domain, SO drives this pin. 2 MSS Master Input SPI Slave Select Input from the Master Controller. This pin is paired with SSS. On the slave domain, this pin drives SSS. This signal uses an active low logic. 3 MGND Master Ground Master Domain Signal Ground Connection. 4 SGND2 Slave Ground Slave Domain Ground Connection. This pin can be left unconnected. 5 SGND1 Slave Ground Slave Domain SPI Isolator Ground. 6 SSS Slave Output SPI Slave Select Output. This pin is paired with MSS. On the master domain, MSS drives this pin. 7 SO Slave Input SPI Data Input Going to the Master MI and SO Line. This pin is paired with MI. On the master domain, this pin drives MI. 8 SI Slave Output SPI Data Output from the Master MO and SI Line. This pin is paired with MO. On the master domain, MO drives this pin. 9 SCK Slave Output SPI Clock Output from the Master. This pin is paired with MCK. On the master domain, MCK drives this pin. 10 SVDD1 Slave Power SPI Isolator Power Supply. Connect a 100 nF decoupling capacitor from SVDD1 to SGND1. 11 to 14, 24 DNC Slave Not applicable Do Not Connect. Do not connect to this pin. to 26 14 SYNC Slave Input SYNC Pin. To synchronize the switching frequency, connect the SYNC pin to an external clock at twice the required switching frequency. Do not leave this pin floating. Connect a 100 kΩ pull-down resistor to SGND2. 15 VOUT2 Slave Power Buck Regulator Output Feedback. 16 SGND2 Slave Ground Slave Power Ground. Ground return for buck regulator output capacitors. 17 SW2 Slave Not applicable Buck Regulator Switch Node. 18 VOUT1 Slave Power Flyback Regulator Output and Overvoltage Sense. Input to buck regulator. 19 FB1 Slave Feedback Node for the Flyback Regulator. 20 SVDD2 Slave Power GPIO Isolators Power Supply. Connect a 100 nF decoupling capacitor from SVDD2 to SGND2. 21 SGPI3 Slave Input General-Purpose Input 3. This pin is paired with MGPO3. 22 SGPO2 Slave Output General-Purpose Output 2. This pin is paired with MGPI2. 23 SGPO1 Slave Output General-Purpose Output 1. This pin is paired with MGPI1. Rev. 0 | Page 10 of 37 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT COMPANION PRODUCTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS REGULATORY INFORMATION ELECTROMAGNECTIC COMPATIBILITY INSULATION AND SAFETY RELATED SPECIFICATIONS DIN V VDE 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION FLYBACK REGULATOR Flyback Regulator Operation Power Saving Mode (PSM) Flyback Undervoltage Lockout (UVLO) Flyback Regulator Precision Enable Control Flyback Regulator Soft Start Flyback Slew Rate Control Flyback Regulator Overcurrent Protection Flyback Regulator Overvoltage Protection BUCK REGULATOR Buck Regulator Operation Buck Regulator UVLO Buck Regulator Soft Start Buck Regulator Current-Limit Protection Buck Regulator Active Pull-Down Resistor Buck Regulator OVP POWER GOOD POWER-UP SEQUENCE OSCILLATOR AND SYNCHRONIZATION THERMAL SHUTDOWN DATA ISOLATION High Speed SPI Channels GPIO Data Channels APPLICATIONS INFORMATION COMPONENT SELECTION Feedback Resistors Capacitor Selection FLYBACK REGULATOR COMPONENTS SELECTION Input Capacitor Output Capacitor Ripple Current vs. Capacitor Value Schottky Diode Transformer Turn Ratio Primary Inductance Flyback Transformer Saturation Current Series Winding Resistance Leakage Inductance and Clamping Circuits Clamping Resistor Clamping Capacitor Clamping Diode Diode, Zener Diode Clamp Ripple Current (IAC) vs. Inductance Maximum Output Current Calculation BUCK REGULATOR COMPONENTS SELECTION Inductor Output Capacitor INSULATION LIFETIME Surface Tracking Insulation Wear Out Calculation and Use of Parameters Example THERMAL ANALYSIS TYPICAL APPLICATION CIRCUIT PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE