Datasheet AD74413R (Analog Devices) - 10

AD74413R Data Sheet DIGITAL INPUT LOGIC
AVDD = 14 V to 28.8 V, AGND = DGND = 0 V, REFIN = 2.5 V (ideal), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to 5.5 V, and all specifications at TA = −40°C to +105°C, unless otherwise noted.
Table 7. Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS

Input Data Rate1 20 kHz Unfiltered input, SENSEL_x pin driven by a low impedance source, 0 V to 10 V signal, duty cycle: 60:40 Maximum Input Voltage1 40 V Limited by the TVS clamping voltage Minimum Input Voltage1 −40 Limited by the TVS clamping voltage CURRENT SINK Range 0 Series Resistor Value 2.3 kΩ Current Sink Range 0 3.7 mA Typical programmable current sink to AGND Current Sink Resolution 120 μA Current Sink Accuracy ±2 %FSR Current Sink at Decimal 2.1 2.4 mA Recommended for IEC61131-2 Type I and Type III for Code 20 I/OP_x screw terminal > 6 V, DIN_SINK = decimal Code 20 Range 1 Series Resistor Value 860 Ω Current Sink Range 0 7.4 mA Typical programmable current sink to AGND Current Sink Resolution 240 μA Current Sink Accuracy ±2 %FSR Current Sink at Decimal 6.1 7.0 mA Recommended for IEC61131-2 Type I and Type III for Code 29 I/OP_x screw terminal > 6 V, DIN_SINK = decimal Code 29 VOLTAGE THRESHOLDS MODES AVDD Threshold Mode Threshold Range AVDD/60 AVDD × 59/60 V Programmable trip level shared between all channels Threshold Resolution AVDD/30 V Hysteresis AVDD/60 V Fixed Threshold Mode Threshold Range 0.5 16 V Programmable trip level shared between all channels Threshold Resolution 0.5 V Hysteresis 0.5 V Threshold Voltage at Decimal 8.2 8.5 8.8 V Rising trip point, recommended for IEC61131-2 Code 16 Type I, Type II, and Type III, COMP_THRESH bits = decimal Code 16 Threshold Accuracy 2 %FSR 1 Guaranteed by design and characterization. Rev. 0 | Page 10 of 70 Document Outline Features Applications General Description Companion Products Product Highlights Revision History Functional Block Diagram Specifications Voltage Output Current Output Voltage Input Current Input Externally Powered and Current Input Externally Powered with HART Current Input Loop Powered Resistance Measurement Digital Input Logic Digital Input Loop Powered ADC Specifications General Specifications Timing Characteristics SPI Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Voltage Output Current Output Digital Input Resistance Measurement Reference ADC Supplies Theory of Operation Robust Architecture Serial Interface DAC Architecture ADC Overview Reference Reference Noise Charge Pump Power-On State of the AD74413R Device Functions High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpreting ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data HART Compatibility Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Thermocouple Measurement Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Externally Powered with HART Compatibility Mode Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered with HART Compatibility Mode Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Threshold Setting Digital Input Current Sink Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter Digital Input Counter Digital Input, Loop Powered Mode Interpreting ADC Data Getting Started Using Channel Functions Switching Channel Functions ADC Functionality ADC Conversion Rates ADC_RDYb Functionality ADC Output Data Format ADC Noise Diagnostics DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control HART Compliant Slew Driving Inductive Loads Reset Function Thermal Alert and Thermal Reset Faults and Alerts Channel Faults Power Supply Monitors GPO_x Pins SPI Interface and Diagnostics SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback Board Design and Layout Considerations Applications Information Register Map NOP Register Function Setup Register per Channel ADC Configuration Register per Channel Digital Input Configuration Register per Channel GPO Parallel Data Register GPO Configuration Register per Channel Output Configuration Register per Channel DAC Code Register per Channel DAC Clear Code Register per Channel DAC Active Code Register per Channel Digital Input Threshold Register ADC Conversion Control Register Diagnostics Select Register Digital Output Level Register ADC Conversion Results Register per Channel Diagnostic Results Registers per Diagnostic Channel Alert Status Register Live Status Register Alert Mask Register Debounced DIN Count Register per Channel Readback Select Register Thermal Reset Enable Register Command Register Scratch or Spare Register Silicon Revision Register Outline Dimensions Ordering Guide