Datasheet AD74412R (Analog Devices) - 10

AD74412R Data Sheet DIGITAL INPUT LOGIC
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT pin tied to REFIN pin), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to 5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted.
Table 7. Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS

Input Data Rate1 5 kHz Unfiltered input, SENSEL pin driven by a low impedance source, 0 V to 10 V signal, duty cycle: 60:40 Maximum Input Voltage1 40 V Limited by the TVS clamping voltage Minimum Input Voltage1 −40 CURRENT SINK Series Resistor Value 2.3 kΩ Current Sink Range 0 1.8 mA Typical programmable current sink to AGND Current Sink Resolution 120 µA Current Sink Accuracy 2 %FSR VOLTAGE THRESHOLDS MODES AVDD Threshold Mode Threshold Range AVDD/60 AVDD × 59/60 V Programmable trip level shared between all channels Threshold Resolution AVDD/30 V Hysteresis AVDD/60 V Fixed Threshold Mode Threshold Range 0.5 16 V Programmable trip level shared between all channels Threshold Resolution 0.5 V Hysteresis 0.5 V Threshold Accuracy 2 %FSR 1 Guaranteed by design and characterization.
DIGITAL INPUT LOOP POWERED
AVDD = 14 V to 26.4 V, AGND = DGND = 0 V, REFIN = 2.5 V (REFOUT pin tied to REFIN pin), DVCC = 2.7 V to 5.5 V, IOVDD = 1.7 V to 5.5 V, and all specifications at TA=−40°C to +85°C, unless otherwise noted.
Table 8. Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS

Input Data Rate1 15 5 kHz Unfiltered input, typical y dominated by wetting current, load capacitance, and threshold voltage Dry Contact Wetting Current 0.5 24.5 mA Loop powered—typical programmable Range current per channel Headroom 5.0 V Minimum required voltage difference between AVDD and the I/OP_x screw terminal to source 25 mA THRESHOLD MODES AVDD Threshold Mode Threshold Range AVDD/60 AVDD × 59/60 V Programmable trip level shared between al channels Threshold Resolution AVDD/30 V Hysteresis AVDD/60 V Fixed Threshold Mode Threshold Range 0.5 16 V Programmable trip level shared between al channels Threshold Resolution 0.5 V Hysteresis 0.5 V Threshold Accuracy 2 %FSR 1 Guaranteed by design and characterization. Rev. A | Page 10 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION COMPANION PRODUCTS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS VOLTAGE OUTPUT CURRENT OUTPUT VOLTAGE INPUT CURRENT INPUT EXTERNALLY POWERED CURRENT INPUT LOOP POWERED RTD MEASUREMENT DIGITAL INPUT LOGIC DIGITAL INPUT LOOP POWERED ADC SPECIFICATIONS GENERAL SPECIFICATIONS TIMING CHARACTERISTICS SPI Timing Specifications Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT CURRENT OUTPUT REFERENCE ADC SUPPLIES THEORY OF OPERATION ROBUST ARCHITECTURE SERIAL INTERFACE DAC ARCHITECTURE ADC OVERVIEW REFERENCE Reference Noise Charge Pump POWER-ON STATE OF THE AD74412R DEVICE FUNCTIONS High Impedance Interpreting ADC Data Voltage Output Mode Voltage Output Short-Circuit Protection Interpretin ADC Data Current Output Mode Current Output Open Circuit Detection Interpreting ADC Data Voltage Input Mode Selectable 200 kΩ to GND Interpreting ADC Data Current Input, Externally Powered Mode Short-Circuit Protection Interpreting ADC Data Current Input, Loop Powered Mode Short-Circuit Protection Interpreting ADC Data Resistance Measurement (External 2-Wire RTD) Interpreting ADC Data Digital Input Logic Interpreting ADC Data Digital Input Current Sink Digital Input Threshold Setting Debounce Function Debounce Mode 0 (Default) Debounce Mode 1 Digital Input Inverter DIGITAL INPUT, LOOP POWERED MODE Interpreting ADC Data GETTING STARTED USING CHANNEL FUNCTIONS Switching Channel Functions ADC FUNCTIONALITY ADC Conversion Rates ADC_RDYB Functionality ADC Output Data Format ADC Noise DIAGNOSTICS DACs LDAC Function Clear Code Function Digital Linear Slew Rate Control DRIVING INDUCTIVE LOADS RESET FUNCTION THERMAL ALERT AND THERMAL RESET FAULTS AND ALERTS Channel Faults POWER SUPPLY MONITORS GPO_x PINS SPI INTERFACE AND DIAGNOSTICS SPI CRC SPI Interface SCLK Count Feature Readback Mode Streaming Mode Auto Readback BOARD DESIGN AND LAYOUT CONSIDERATIONS APPLICATIONS INFORMATION REGISTER MAP NOP REGISTER FUNCTION SETUP REGISTER PER CHANNEL ADC CONFIGURATION REGISTER PER CHANNEL DIGITAL INPUT CONFIGURATION REGISTER PER CHANNEL GPO PARALLEL DATA REGISTER GPO CONFIGURATION REGISTER PER CHANNEL OUTPUT CONFIGURATION REGISTER PER CHANNEL DAC CODE REGISTER PER CHANNEL DAC CLEAR CODE REGISTER PER CHANNEL DAC ACTIVE CODE REGISTER PER CHANNEL DIGITAL INPUT THRESHOLD REGISTER ADC CONVERSION CONTROL REGISTER DIAGNOSTICS SELECT REGISTER DIGITAL OUTPUT LEVEL REGISTER ADC CONVERSION RESULTS REGISTER PER CHANNEL DIAGNOSTIC RESULTS REGISTERS PER DIAGNOSTIC CHANNEL ALERT STATUS REGISTER LIVE STATUS REGISTER ALERT MASK REGISTER READBACK SELECT REGISTER 80 SPS ADC CONVERSION CONTROL REGISTER THERMAL RESET ENABLE REGISTER COMMAND REGISTER SCRATCH OR SPARE REGISTER SILICON REVISION REGISTER OUTLINE DIMENSIONS ORDERING GUIDE