Datasheet AD7294-2 (Analog Devices) - 25

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Data Sheet AD7294-2 REGISTER SETTINGS
The AD7294-2 contains internal registers (see Figure 46) that
ADDRESS POINTER REGISTER
store conversion results, high and low conversion limits, and The address pointer register is an 8-bit register in which the information to configure and control the device. six LSBs are used as pointer bits to store an address that points
COMMAND
to one of the AD7294-2 data registers (see Table 9).
REGISTER ADC RESULT Table 9. Register Addresses REGISTER Address Register Name Access DAC REGISTERS
0x00 Command register W
T
0x01 ADC result register R
SENSE RESULT REGISTERS × 3
DACA value W
ALERT STATUS
0x02 TSENSE1 result R
REGISTERS × 3
DACB value W
CHANNEL A SEQUENCE ADDRESS
0x03 TSENSE2 result R
REGISTER POINTER DAT REGISTER CONFIGURATION
DACC value W
REGISTER
0x04 TSENSEINT result R
POWER-DOWN
DACD value W
REGISTER
0x05 Alert Status Register A R/W
DATAHIGH/ DATALOW REGISTERS × 18
0x06 Alert Status Register B R/W
HYSTERESIS
0x07 Alert Status Register C R/W
REGISTERS × 9
0x08 Channel sequence register R/W
TSENSE OFFSET
0x09 Configuration register R/W
REGISTERS × 2
0x0A Power-down register R/W 039
SERIAL BUS INTERFACE SDA SCL
10936- 0x0B DATALOW Register VIN0 R/W Figure 46. Register Structure 0x0C DATAHIGH Register VIN0 R/W Each data register has an address to which the address pointer 0x0D Hysteresis Register VIN0 R/W register points when communicating with it. The command 0x0E DATALOW Register VIN1 R/W register is the only register that is a write only register; the 0x0F DATAHIGH Register VIN1 R/W remainder of the addresses have both read and write access. 0x10 Hysteresis Register VIN1 R/W 0x11 DATALOW Register VIN2 R/W 0x12 DATAHIGH Register VIN2 R/W 0x13 Hysteresis Register VIN2 R/W 0x14 DATALOW Register VIN3 R/W 0x15 DATAHIGH Register VIN3 R/W 0x16 Hysteresis Register VIN3 R/W 0x17 DATALOW Register ISENSE1 R/W 0x18 DATAHIGH Register ISENSE1 R/W 0x19 Hysteresis Register ISENSE1 R/W 0x1A DATALOW Register ISENSE2 R/W 0x1B DATAHIGH Register ISENSE2 R/W 0x1C Hysteresis Register ISENSE2 R/W 0x1D DATALOW Register TSENSE1 R/W 0x1E DATAHIGH Register TSENSE1 R/W 0x1F Hysteresis Register TSENSE1 R/W 0x20 DATALOW Register TSENSE2 R/W 0x21 DATAHIGH Register TSENSE2 R/W 0x22 Hysteresis Register TSENSE2 R/W 0x23 DATALOW Register TSENSEINT R/W 0x24 DATAHIGH Register TSENSEINT R/W 0x25 Hysteresis Register TSENSEINT R/W 0x26 TSENSE1 offset register R/W 0x27 TSENSE2 offset register R/W 0x40 Factory test mode N/A 0x41 Factory test mode N/A Rev. 0 | Page 25 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide