Datasheet ADAS1000, ADAS1000-1, ADAS1000-2 (Analog Devices) - 4

FabricanteAnalog Devices
DescripciónLow Power, Five Electrode Electrocardiogram (ECG) Analog Front End
Páginas / Página85 / 4 — ADAS1000/. ADAS1000-1/. ADAS1000-2. Data Sheet. FUNCTIONAL BLOCK DIAGRAM. …
RevisiónC
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Idioma del documentoInglés

ADAS1000/. ADAS1000-1/. ADAS1000-2. Data Sheet. FUNCTIONAL BLOCK DIAGRAM. REFIN REFOUT. CAL_DAC_IO. RLD_SJ. RLD_OUT CM_IN. CM_OUT/WCT

ADAS1000/ ADAS1000-1/ ADAS1000-2 Data Sheet FUNCTIONAL BLOCK DIAGRAM REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN CM_OUT/WCT

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ADAS1000/ ADAS1000-1/ ADAS1000-2 Data Sheet FUNCTIONAL BLOCK DIAGRAM REFIN REFOUT CAL_DAC_IO RLD_SJ RLD_OUT CM_IN CM_OUT/WCT SHIELD AVDD IOVDD DRIVEN LEAD SHIELD VREF AMP DRIVE ADCVDD ADCVDD, DVDD AMP 1.8V CALIBRATION DVDD + REGULATORS DAC VCM_REF (1.3V) RESPIRATION DAC COMMON- MODE AMP AC LEAD-OFF DAC AC LEAD-OFF 10kΩ DETECTION BUFFER PACE CS MUXES DETECTION 5× ECG PATH SCLK ELECTRODES SDI ×5 FILTERS, AMP ADC CONTROL, SDO AND INTERFACE DRDY LOGIC GPIO0/MCS GPIO1/MSCLK GPIO2/MSDO EXT_RESP_LA GPIO3 AMP ADC EXT_RESP_LL EXT_RESP_RA CLOCK GEN/OSC/ RESPIRATION PATH EXTERNAL CLK CLK_IO ADAS1000 SOURCE
001
XTAL1 XTAL2
09660- Figure 1. ADAS1000 Full Featured Model
Table 1. Overview of Features Available from ADAS1000 Ge nerics Pace Shield Master Package Generic1 ECG Operation Right Leg Drive Respiration Detection Driver Interface2 Option
ADAS1000 5 ECG channels Master/slave Yes Yes Yes Yes Yes LFCSP, LQFP ADAS1000-1 5 ECG channels Master/slave Yes Yes Yes LFCSP ADAS1000-2 5 ECG channels Slave LFCSP, LQFP ADAS1000-3 3 ECG channels Master/slave Yes Yes Yes LFCSP, LQFP ADAS1000-4 3 ECG channels Master/slave Yes Yes Yes Yes Yes LFCSP, LQFP 1 The ADAS1000-2 is a companion device for increased channel count purposes. It has a subset of features and is not intended for standalone use. It can be used in conjunction with any master device. 2 Master interface is provided for users wishing to utilize their own digital pace algorithm; see the Secondary Serial Interface section. Rev. C | Page 4 of 85 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Noise Performance Timing Characteristics Standard Serial Interface Secondary Serial Interface (Master Interface for Customer-Based Digital Pace Algorithm) ADAS1000/ADAS1000-1 Only Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Applications Information Overview ECG Inputs—Electrodes/Leads ECG Channel Electrode/Lead Formation and Input Stage Configuration Analog Lead Mode and Calculation Digital Lead Mode and Calculation Electrode Mode: Single-Ended Input Electrode Configuration Electrode Mode: Common Electrode A and Electrode B Configurations Defibrillator Protection ESIS Filtering ECG Path Input Multiplexing Common-Mode Selection and Averaging Wilson Central Terminal (WCT) Right Leg Drive/Reference Drive Calibration DAC Gain Calibration Lead-Off Detection DC Lead-Off Detection DC Lead-Off and High Gains DC Lead-Off Debounce Timer AC Lead-Off Detection ACLO and Common-Mode Configuration ADC Out of Range Shield Driver Respiration (ADAS1000 Model Only) Internal Respiration Capacitors External Respiration Path External Respiration Capacitors Respiration Carrier Frequency Evaluating Respiration Performance Extend Switch On Respiration Paths Pacing Artifact Detection Function (ADAS1000 Only) Choice of Leads Detection Algorithm Overview Pace Edge Threshold Pace Level Threshold Pace Amplitude Threshold Pace Validation Filters Pace Width Filter Biventricular Pacers Pace Detection Measurements Evaluating Pace Detection Performance Pace Width Pace Latency Pace Detection via Secondary Serial Interface (ADAS1000 and ADAS1000-1 Only) Filtering Voltage Reference Gang Mode Operation Master/Slave Synchronizing Devices Calibration Common Mode Right Leg Drive Sequencing Devices into Gang Mode Number of Devices in Gang Mode Interfacing in Gang Mode Serial Interfaces Standard Serial Interface Write Mode Write/Read Data Format Data Frames/Packets Read Mode Serial Clock Rate Data Rate and Skip Mode Data Ready (DRDYB) Detecting Missed Conversion Data SPI Interface Resync CRC Word Clocks Secondary Serial Interface RESETB PDB Function SPI Output Frame Structure (ECG and Status Data) SPI Register Definitions and Memory Map Control Registers Details Examples of Interfacing to the ADAS1000 Example 1: Initialize the ADAS1000 for ECG Capture and Start Streaming Data Example 2: Enable Respiration and Stream Conversion Data Example 3: DC Lead-Off and Stream Conversion Data Example 4: Configure 150 Hz Test Tone Sine Wave on Each ECG Channel and Stream Conversion Data Example 5: Enable Pace Detection and Stream Conversion Data Example 6: Writing to Master and Slave Devices and Streaming Conversion Data Slave Configuration Master Configuration Software Flowchart Power Supply, Grounding, and Decoupling Strategy AVDD ADCVDD and DVDD Supplies Unused Pins/Paths Layout Recommendations Outline Dimensions Ordering Guide