Datasheet ADUCM355 (Analog Devices) - 17

Data Sheet ADuCM355 Timing Diagrams CS t t CS SFS SCLK (POLARITY = 0) tSH tSL SCLK (POLARITY = 1) tDAV MOSI MSB BIT 6 TO BIT 1 LSB MISO MSB IN BIT 6 TO BIT 1 LSB IN tDSU
-003
tDHD
674 16 Figure 3. SPI Master Timing Diagram (Phase Mode = 1)
CS tSFS tCS SCLK (POLARITY = 0) tSH tSL SCLK (POLARITY = 1) tDAV tDOSU MISO MSB BIT 6 TO BIT 1 LSB MOSI MSB IN BIT 6 TO LSB IN BIT 1 tDSU
004 4-
tDHD
1667 Figure 4. SPI Master Timing Diagram (Phase Mode = 0) Rev. C | Page 17 of 28 Document Outline FEATURES APPLICATIONS SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION SPECIFICATIONS MICROCONTROLLER ELECTRICAL SPECIFICATIONS RMS NOISE RESOLUTION OF ADC TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION RECOMMENDED CIRCUIT AND COMPONENT VALUES OUTLINE DIMENSIONS ORDERING GUIDE