Datasheet HIP2210, HIP2211 (Renesas) - 6
| Fabricante | Renesas |
| Descripción | 100V, 3A Source, 4A Sink, High Frequency Half-Bridge Drivers with Tri-Level PWM Input and Adjustable Dead Time |
| Páginas / Página | 28 / 6 — Specifications. 2.1. Absolute Maximum Ratings. Parameter (Note 5). … |
| Formato / tamaño de archivo | PDF / 608 Kb |
| Idioma del documento | Inglés |
Specifications. 2.1. Absolute Maximum Ratings. Parameter (Note 5). Minimum. Maximum. Unit. ESD Ratings. Value. CAUTION:. Note:. 2.2
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2. Specifications 2.1 Absolute Maximum Ratings Parameter (Note 5) Minimum Maximum Unit
Supply Voltage, VDD -0.3 +20 V Boot Voltage, HB Referenced to HS -0.3 +20 V Bootstrap Voltage, HB Referenced to VSS -0.3 +120 V Bootstrap Voltage, HB Referenced to VDD -0.3 +110 V Continuous Voltage on HS The greater of +120 V [-10 or -(20 - VDD)] EN, HI, and LI Voltage -0.3 VDD + 0.3 V PWM, VREF, RDT Voltage -0.3 +6 V Voltage on LO -0.3 VDD + 0.3 V Transient Voltage on LO (Repetitive Transient for 100ns) -2 - V Voltage on HO VHS - 0.3 VHB + 0.3 V Transient Voltage on HO (Repetitive Transient for 100ns) VHS - 2 - V
ESD Ratings Value Unit
Human Body Model (Tested per JS-001-2017) 2.5 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA
CAUTION:
Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
Note:
5. All voltages referenced to VSS unless otherwise specified.
2.2 Thermal Information Thermal Resistance (Typical) Max Power Dissipation at +25°C Package Type θJA (°C/W)
8 Ld SOIC (Notes 8, 9) 102
θJC (°C/W) in Free Air (W) (Note 10)
50 1.22 10 Ld TDFN, 8 Ld DFN (Notes 6, 7) 40 2.5 3.12
Notes:
6. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 7. For θJC, the case temperature location is the center of the exposed metal pad on the package underside. 8. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379. 9. For θJC, the case temperature location is taken at the package top center. 10. Specified at published junction to ambient thermal resistance for a junction temperature of +150°C. See Note 6 for test condition to establish junction to ambient thermal resistance.
Parameter Minimum Maximum Unit
Maximum Junction Temperature -65 +150 °C Maximum Storage Temperature Range -55 +140 °C Pb-Free Reflow Profile see TB493 FN9347 Rev.1.01 Page 6 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings
2. Specifications 2.1 Absolute Maximum Ratings Parameter (Note 5) Minimum Maximum Unit
Supply Voltage, VDD -0.3 +20 V Boot Voltage, HB Referenced to HS -0.3 +20 V Bootstrap Voltage, HB Referenced to VSS -0.3 +120 V Bootstrap Voltage, HB Referenced to VDD -0.3 +110 V Continuous Voltage on HS The greater of +120 V [-10 or -(20 - VDD)] EN, HI, and LI Voltage -0.3 VDD + 0.3 V PWM, VREF, RDT Voltage -0.3 +6 V Voltage on LO -0.3 VDD + 0.3 V Transient Voltage on LO (Repetitive Transient for 100ns) -2 - V Voltage on HO VHS - 0.3 VHB + 0.3 V Transient Voltage on HO (Repetitive Transient for 100ns) VHS - 2 - V
ESD Ratings Value Unit
Human Body Model (Tested per JS-001-2017) 2.5 kV Charged Device Model (Tested per JS-002-2014) 1 kV Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA
CAUTION:
Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
Note:
5. All voltages referenced to VSS unless otherwise specified.
2.2 Thermal Information Thermal Resistance (Typical) Max Power Dissipation at +25°C Package Type θJA (°C/W)
8 Ld SOIC (Notes 8, 9) 102
θJC (°C/W) in Free Air (W) (Note 10)
50 1.22 10 Ld TDFN, 8 Ld DFN (Notes 6, 7) 40 2.5 3.12
Notes:
6. θJA is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379. 7. For θJC, the case temperature location is the center of the exposed metal pad on the package underside. 8. θJA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379. 9. For θJC, the case temperature location is taken at the package top center. 10. Specified at published junction to ambient thermal resistance for a junction temperature of +150°C. See Note 6 for test condition to establish junction to ambient thermal resistance.
Parameter Minimum Maximum Unit
Maximum Junction Temperature -65 +150 °C Maximum Storage Temperature Range -55 +140 °C Pb-Free Reflow Profile see TB493 FN9347 Rev.1.01 Page 6 of 27 Jun.23.20 Document Outline Related Literature Features Applications Contents 1. Overview 1.1 Block Diagrams 1.2 Ordering Information 1.3 Pin Configurations 1.4 Pin Descriptions 2. Specifications 2.1 Absolute Maximum Ratings 2.2 Thermal Information 2.3 Recommended Operating Conditions 2.4 Electrical Specifications 2.5 Switching Specifications 2.6 Timing Diagrams 3. Typical Performance Curves 4. Functional Description 4.1 Gate Drive for NMOS Half-Bridge 4.2 Functional Overview 5. Applications Information 5.1 HI/LI Input Control (HIP2211 Only) 5.2 PWM Input Control (HIP2210 Only) 5.3 VREF Input (HIP2210 Only) 5.4 EN Pin (HIP2210 Only) 5.5 Power Sequencing HIP2210 5.6 Selecting the Boot Capacitor Value 5.7 VDD Decoupling Capacitor 5.8 RDT and Dead Time Delay (HIP2210 Only) 5.9 HO and LO Outputs 5.10 Power Dissipation 5.10.1 Gate Power (for the HO and LO Outputs) 5.10.2 Boot Diode Dissipation 5.10.3 Dynamic Operating Current 5.10.4 Total Power Dissipation 5.10.5 Junction Operating Temperature 6. PCB Layout Guidelines 6.1 PCB Layout and EPAD Recommendation 7. Revision History 8. Package Outline Drawings