Datasheet ADL5902 (Analog Devices) - 26

ADL5902 Data Sheet EVALUATION BOARD SCHEMATICS AND ARTWORK VPOS +5V GND C3 (RED) C7 (BLACK) 0.1µF 0.1µF C4 C5 100pF 100pF TEMP (BLACK) VPOS POS 3 10 VSET ADL5902 TEMPERATURE TEMP 8 (BLACK) SENSOR C10 VSET 7 100pF INHI R2 RFIN 14 IDET OPEN R3 INLO X2 60.4Ω 15 C12 LINEAR-IN-dB VGA 100pF R6 (NEGATIVE SLOPE) 0Ω X2 ITGT R1 NC 2 VOUT 0Ω G = 5 6 VOUT (BLACK) R15 OPEN NC 16 BIAS AND POWER- VREF DOWN CONTROL 2.3V CLPF NC 5 13 C9 26pF 10µF 1 11 12 9 4 TADJ/PWDN VREF VTGT COMM COMM TC2 PWDN (BLACK) R9 R10 VTGT R12 1430Ω 3.74kΩ (BLACK) 301Ω R11 2kΩ
0
VREF
-15
(BLACK)
218 08 Figure 54. Evaluation Board Schematic
Table 8. Evaluation Board Configuration Options Component Function/Notes Default Value
C10, C12, R3 RF input. The ADL5902 is generally driven single-ended. R3 is the input termination resistor and is C10 = C12 = 100 pF chosen to give a 50 Ω input impedance over a broad frequency range. R3 = 60.4 Ω R10, R11 VTGT interface. R10 and R11 are set up to provide 0.8 V to VTGT derived from VREF. R10 = 3.74 kΩ, R11 = 2 kΩ C4, C5, C7, C3 Power supply decoupling. The nominal supply decoupling consists of two pairs of 100 pF and C4 = C5 = 100 pF, 0.1 μF capacitors placed close to the two power supply pins of the ADL5902. C7 = C3 = 0.1 μF R1, R15, R2, Output interface. In measurement mode, a portion of the voltage at the VOUT pin is fed back to R1 = R6= 0 Ω, R6 the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude of the slope R2 = R15 = open of VOUT is increased by reducing the portion of VOUT that is fed back to VSET. In controller mode, R6 must be open. In this mode, the ADL5902 can control the gain of an external component. A setpoint voltage is applied to the VSET pin, the value of which corresponds to the desired RF input signal level applied to the ADL5902. C9 Low-pass filter capacitors, CLPF. The low-pass filter capacitor provides the averaging for the C9 = 0.1 μF ADL5902 rms computation. R9, R12 TADJ/PWDN. The TADJ/PWDN pin controls the amount of nonlinear intercept temperature R9 = 1430 Ω compensation and/or shuts down the device. The evaluation board is configured with TADJ R12 = 301 Ω connected to VREF through a resistor divider (R9, R12). Rev. B | Page 26 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION SQUARE LAW DETECTOR AND AMPLITUDE TARGET RF INPUT INTERFACE SMALL SIGNAL LOOP RESPONSE TEMPERATURE SENSOR INTERFACE VREF INTERFACE TEMPERATURE COMPENSATION INTERFACE POWER-DOWN INTERFACE VSET INTERFACE OUTPUT INTERFACE VTGT INTERFACE BASIS FOR ERROR CALCULATIONS MEASUREMENT MODE BASIC CONNECTIONS SETTING VTADJ SETTING VTGT CHOOSING A VALUE FOR CLPF OUTPUT VOLTAGE SCALING SYSTEM CALIBRATION AND ERROR CALCULATION HIGH FREQUENCY PERFORMANCE LOW FREQUENCY PERFORMANCE DESCRIPTION OF CHARACTERIZATION EVALUATION BOARD SCHEMATICS AND ARTWORK ASSEMBLY DRAWINGS OUTLINE DIMENSIONS ORDERING GUIDE