Datasheet ADRV9002 (Analog Devices) - 63

link to page 63
Preliminary Technical Data ADRV9002 RECEIVER
The receiver includes two ADC pairs. One pair is of high Figure 200 shows a simplified block diagram of the ADRV9002 performance Σ-Δ ADCs to provide maximum interferer receiver. It is a fully integrated, direct conversion, low IF receiver tolerance and the second pair is of ADCs for significant power signal chain. The receiver subsystem consists of a resistive input reduction. The extra pair of ADCs allow a smart tradeoff network for gain control followed by a current mode passive between power and performance. mixer. The output current of the mixer is converted to a voltage The ADC output can be conditioned further by a series of by a transimpedance amplifier and then digitized. There are decimation filters and a fully programmable, 128-tap FIR filter two sets of ADCs, a high performance Σ-Δ ADC and a low with additional decimation settings. The sample rate of each power ADC. The digital baseband that provides the required digital filter block automatically adjusts with each change of the filtering and decimation follows these ADCs. decimation factors to produce the desired output data rate. There are two RF inputs for each receiver to match to different For standards that demand low phase noise performance, the bands in one reference design. The mixer architecture is linear ADRV9002 can operate in low-IF mode. The ADRV9002 can and inherently wideband, which facilitates impedance matching. receive signals offset from the carrier, as with an IF The differential input impedance of the receiver inputs is 100 Ω. downconversion scheme. A digital NCO and mixer that follow To achieve gain control, a programmed gain index map is the analog receive path can downconvert the IF signal to implemented. This gain map distributes attenuation among the baseband. Downconverting the signal down to baseband allows various receiver blocks for optimal performance at each power a lower sample rate on the data bus. The ADRV9002 makes no level. The gain range is 36 dB with 0.5 dB steps. Additional support assumptions about high-side or low-side injection. is available for both automatic and manual gain control modes.
Monitor Mode
The receive LPFs can be reconfigured to help provide antialias The ADRV9002 receive signal chain can be configured to filtering and improve out of band blockers. The ADRV9002 is a monitor the radio channel signal level in duty cycle detection wideband architecture transceiver that relies on the ADC high and sleep fashion. Monitor mode allows the digital baseband dynamic range to receive signal and interference at the same processor to power down until the ADRV9002 detect a signal. time. Filtering provided by the receive LPF attenuates ADC Monitor mode provides overall system power saving. The alias images. The receive LPF characteristic is flat and not timing of detection and sleep mode is fully programmable. intended to provide rejection of close in blockers. The baseband Alternatively, the ADRV9002 can be under full control of the filter supports a baseband bandwidth from 5 MHz to 50 MHz. baseband processor during monitor mode.
Rx1/ Rx2 RX1A+, 2 RX2A+ HP DIGITAL SIGNAL PROCESSING: RX1/2_DCLK_OUT(±) RX1A–, ADC LPF – DECIMATION RX2A– – DC OFFSET CORRECTION (DC) 2 LP – QUADRATURE ERROR CORRECTION (QEC) 0° ADC – DIGITAL DOWNCONVERSION DATA RX1/2_STROBE_OUT(±) RX1B+, 90° – PROGRAMMABLE FIR FILTER (pFIR) PORT RX2B+ LP – AUTOMATIC GAIN CONTROL (AGC) 2 RX1B–, ADC – RECEIVER SIGNAL STRENGTH INDICATOR (RSSI) RX1/2_IDATA_OUT(±) RX2B– – OVERLOAD DETECTORS HP – INTERFACE GAIN 2 LPF ADC – FSK DISCRIMINATION AND SYNC DETECTION RX1/2_QDATA_OUT(±)
1
INTERNAL LO
-20
OBSERVATION
663 24 Figure 200. Receiver Architecture Rev. PrA | Page 63 of 71 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TRANSMITTER SPECIFICATIONS RECEIVER SPECIFICATIONS INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK DIGITAL INTERFACES AND AUXILIARY CONVERTERS POWER SUPPLY SPECIFICATIONS CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES) Sleep Mode (Typical Values) TDD Operation (Typical Values) FDD Operation (Typical Values) TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADRV2009 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 30 MHZ BAND 470 MHZ BAND 900 MHZ BAND 2400 MHZ BAND 3500 MHZ BAND 5800 MHZ BAND PHASE NOISE THEORY OF OPERATION TRANSMITTER RECEIVER Monitor Mode DPD Receiver as an Observation Receiver CLOCK INPUT SYNTHESIZERS RF PLL Baseband PLL (PLL) SPI INTERFACE GPIO PINS Digital GPIO Inputs/Outputs (DGPIO) Analog GPIO Inputs/Outputs (AGPIO) AUXILLARY CONVERTERS Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs Outputs (AUXDAC_x) JTAG BOUNDARY SCAN APPLICATIONS INFORMATION POWER SUPPLY SEQUENCE DIGITAL DATA INTERFACE CSSI CSSI Receive CSSI Transmit LSSI OUTLINE DIMENSIONS