Datasheet ADRV9002 (Analog Devices) - 64

ADRV9002 Preliminary Technical Data DPD CLOCK INPUT
The ADRV9002 provides a fully integrated DPD function that The reference clock inputs provide a low frequency clock from alters the digital waveform to compensate for nonlinearities in which all internal ADRV9002 clocks for the are derived. The the power amplifier response, which linearizes the output of the ADRV9002 offers multiple reference input clocking options. power amplifier of the transmit system. The internal DPD The reference input clock pins on the device are labeled block is optimized for both narrowband and wideband signals. DEV_CLK_IN±. The DPD actuator and coefficient calculation engine are both For optimal performance, drive the reference clock integrated. This functionality uses the receive channel to differentially via an external source or from an external crystal. monitor the output of the power amplifier and calculates the If a differential input clock is provided, the clock signal must be appropriate predistortion to linearize the output. The ac-coupled with the input range limited from 10 MHz to integrated DPD capability allows the system to drive the power 1 GHz. The ADRV9002 can also accept an external crystal amplifier closer to saturation, enabling a higher efficiency (XTAL) as a clock source. The frequency range of the power amplifier while maintaining linearity. supported crystal is between 20 MHz to 80 MHz. The external
Receiver as an Observation Receiver
crystal connection must be dc-coupled. In FDD type applications where only one receiver is used or in If a differential clock is not available, a single ended ac-coupled V the TDD type applications during transmitter time slots, pk-pk (maximum) CMOS signal can be applied to the unused receiver inputs can be used to perform transmitter DEV_CLK_IN+ pin with the DEV_CLK_IN− pin unconnected. observation. The observation receiver operates in a similar The maximum clock frequency in this mode is limited to 80 MHz. manner to the main receivers.
SYNTHESIZERS
Use the observation receiver channel for the following: The ADRV9002 offers two distinct PLL paths, an RF PLL for Monitor the transmitter channels and implement the high frequency RF path and a baseband PLL for the digital transmitter LOL correction and transmitter QEC. and sampling clocks of the data converters. Monitor signal levels after the power amplifier output.
RF PLL
This data can be used by a fully integrated low power DPD The PLL structure in the ADRV9002 is quite unique in the block. The integrated DPD is optimized for both sense that instead of having one dedicated PLL for the receive narrowband and wideband signals and enables and a dedicated PLL for the transmit, two RF PLLs are in the linearization of high efficiency power amplifiers. device and both PLLs can source the receiver, the transmitter, Monitor signal levels after the power amplifier output for both paths, or neither. This flexibility enables the ADRV9002 to further data processing in the external baseband processor. meet various applications that require versatility. In cases where the observation receiver path is used for DPD The RF PLL supports the use of both internal and external LO operation, there is a limit to the maximum bandwidth of the signals. The internal LO is generated by an on-chip VCO, which is transmitter signal the DPD can support. For example, if the tunable over a frequency range of 6.5 GHz to 13 GHz. The DPD observation factor is 5×, the transmitter signal bandwidth output of the VCO is phase-locked to an external reference clock is limited to 1/5 of the DPD observation BANDWIDTH. When through a fractional-N PLL that is programmable through the API utilizing the ADRV9002 internal DPD block, because of the command. The VCO outputs are steered through a combination large internal DPD observation bandwidth of 100 MHz, the of frequency dividers to produce in-phase and quadrature largest transmitter bandwidth that the internal DPD can phase LO signals in the 30 MHz to 6 GHz frequency range. support is 20 MHz. When external DPD is used, the largest DPD observation bandwidth is limited by the transmitter and Alternatively, an external 2× or more LO signal can be applied observation receiver RF bandwidth. 40 MHz is largest RF to the external LO inputs of the ADRV9002 to generate the LO bandwidth that can be received and sent over digital data port signals in quadrature for the RF path. If the external LO path is to the baseband processor, which implies that 8 MHz chosen, the input frequency range is between 60 MHz to 12 GHz. represents the largest transmitter bandwidth that the DPD PLL synthesizers are fractional-N designs that incorporate implemented externally to the ADRV9002 can support. completely integrated VCOs and loop filters. In TDD operation, LO distribution paths and receive/transmit data paths turn on and off as appropriate for the receive and transmit frames. In FDD mode, the transmit PLL and the receive PLL can be activated simultaneously. These PLLs require no external components. The RF LO generation circuits enable the user to choose between a high performance or low power mode of operation. Rev. PrA | Page 64 of 71 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TRANSMITTER SPECIFICATIONS RECEIVER SPECIFICATIONS INTERNAL LO, EXTERNAL LO, AND DEVICE CLOCK DIGITAL INTERFACES AND AUXILIARY CONVERTERS POWER SUPPLY SPECIFICATIONS CURRENT CONSUMPTION ESTIMATES (TYPICAL VALUES) Sleep Mode (Typical Values) TDD Operation (Typical Values) FDD Operation (Typical Values) TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ELECTROSTATIC DISCHARGE (ESD) RATINGS ESD Ratings for ADRV2009 ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 30 MHZ BAND 470 MHZ BAND 900 MHZ BAND 2400 MHZ BAND 3500 MHZ BAND 5800 MHZ BAND PHASE NOISE THEORY OF OPERATION TRANSMITTER RECEIVER Monitor Mode DPD Receiver as an Observation Receiver CLOCK INPUT SYNTHESIZERS RF PLL Baseband PLL (PLL) SPI INTERFACE GPIO PINS Digital GPIO Inputs/Outputs (DGPIO) Analog GPIO Inputs/Outputs (AGPIO) AUXILLARY CONVERTERS Auxiliary ADC Inputs (AUXADC_x) Auxiliary DACs Outputs (AUXDAC_x) JTAG BOUNDARY SCAN APPLICATIONS INFORMATION POWER SUPPLY SEQUENCE DIGITAL DATA INTERFACE CSSI CSSI Receive CSSI Transmit LSSI OUTLINE DIMENSIONS