Datasheet TLE7272-2E (Infineon) - 4

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TLE7272-2 Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-SSOP-14 Exposed Pad
QF QF 52 , QF QF *1' QF QF QF (1 4 QF QF 7/(B3,1&21),*B6623 69*
Figure 2 Pin Configuration (top view) 3.2 Pin Definitions and Functions PG-SSOP-14 Exposed Pad Pin No. Symbol Function
1,3,5,7 n.c.
non connected
can be open or connected to GND 2 RO
Reset Output
open collector output with integrated pull-up resistor; optional external pull-up resistor of ≥ 10 kΩ to pin Q; leave open if reset function not needed 4 GND
Ground
6 EN
Enable Input
high level input signal enables the IC; low level input signal disables the IC; integrated pull-down resistor 8,10,11,12,14 n.c.
non connected
can be open or connected to GND 9 Q
Output
block to ground with a capacitor close to the IC terminals, respecting the values given for its capacitance and ESR in
“Functional Range” on Page 6
13 I
Input
block to ground directly at the IC with a ceramic capacitor Pad –
Exposed Pad
connect to GND and heatsink area Data Sheet 4 Rev. 1.0, 2009-06-01 Document Outline 1 Overview 2 Block Diagram 3 Pin Configuration 3.1 Pin Assignment PG-SSOP-14 Exposed Pad 3.2 Pin Definitions and Functions PG-SSOP-14 Exposed Pad 3.3 Pin Assignment PG-TO252-5 3.4 Pin Definitions and Functions PG-TO252-5 4 General Product Characteristics 4.1 Absolute Maximum Ratings 4.2 Functional Range 4.3 Thermal Resistance 5 Electrical Characteristics 5.1 Electrical Characteristics Voltage Regulator 5.2 Typical Performance Characteristics Voltage Regulator 5.3 Electrical Characteristics Enable Function 5.4 Typical Performance Characteristics Enable Function 5.5 Electrical Characteristics Reset Function 5.6 Typical Performance Characteristics Reset Function 6 Package Outlines 7 Revision History