Datasheet ADCMP600, ADCMP601, ADCMP602 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparators |
| Páginas / Página | 16 / 2 — ADCMP600/ADCMP601/ADCMP602. TABLE OF CONTENTS. REVISION HISTORY 1/11—Rev. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 291 Kb |
| Idioma del documento | Inglés |
ADCMP600/ADCMP601/ADCMP602. TABLE OF CONTENTS. REVISION HISTORY 1/11—Rev. 0 to Rev. A. 10/06—Revision 0: Initial Version
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ADCMP600/ADCMP601/ADCMP602 TABLE OF CONTENTS
Features .. 1 Application Information .. 10 Applications ... 1 Power/Ground Layout and Bypassing ... 10 Functional Block Diagram .. 1 TTL-/CMOS-Compatible Output Stage ... 10 General Description ... 1 Using/Disabling the Latch Feature ... 10 Revision History ... 2 Optimizing Performance ... 11 Specifications ... 3 Comparator Propagation Delay Dispersion ... 11 Electrical Characteristics ... 3 Comparator Hysteresis .. 11 Timing Information ... 5 Crossover Bias Point .. 12 Absolute Maximum Ratings .. 6 Minimum Input Slew Rate Requirement .. 12 Thermal Resistance .. 6 Typical Application Circuits ... 13 ESD Caution .. 6 Outline Dimensions ... 14 Pin Configuration and Function Descriptions ... 7 Ordering Guide .. 16 Typical Performance Characteristics ... 8
REVISION HISTORY 1/11—Rev. 0 to Rev. A
Changed VEE Pin to GND ... Throughout Changes to Common-Mode Dispersion Conditions... 4 Changes to Figure 15 and Figure 16 ... 9 Changes to Comparator Hysteresis Section .. 12 Updated Outline Dimensions ... 14 Changes to Ordering Guide .. 15
10/06—Revision 0: Initial Version
Rev. A | Page 2 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Timing Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Information Power/Ground Layout and Bypassing TTL-/CMOS-Compatible Output Stage Using/Disabling the Latch Feature Optimizing Performance Comparator Propagation Delay Dispersion Comparator Hysteresis Crossover Bias Point Minimum Input Slew Rate Requirement Typical Application Circuits Outline Dimensions Ordering Guide
ADCMP600/ADCMP601/ADCMP602 TABLE OF CONTENTS
Features .. 1 Application Information .. 10 Applications ... 1 Power/Ground Layout and Bypassing ... 10 Functional Block Diagram .. 1 TTL-/CMOS-Compatible Output Stage ... 10 General Description ... 1 Using/Disabling the Latch Feature ... 10 Revision History ... 2 Optimizing Performance ... 11 Specifications ... 3 Comparator Propagation Delay Dispersion ... 11 Electrical Characteristics ... 3 Comparator Hysteresis .. 11 Timing Information ... 5 Crossover Bias Point .. 12 Absolute Maximum Ratings .. 6 Minimum Input Slew Rate Requirement .. 12 Thermal Resistance .. 6 Typical Application Circuits ... 13 ESD Caution .. 6 Outline Dimensions ... 14 Pin Configuration and Function Descriptions ... 7 Ordering Guide .. 16 Typical Performance Characteristics ... 8
REVISION HISTORY 1/11—Rev. 0 to Rev. A
Changed VEE Pin to GND ... Throughout Changes to Common-Mode Dispersion Conditions... 4 Changes to Figure 15 and Figure 16 ... 9 Changes to Comparator Hysteresis Section .. 12 Updated Outline Dimensions ... 14 Changes to Ordering Guide .. 15
10/06—Revision 0: Initial Version
Rev. A | Page 2 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Timing Information Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Information Power/Ground Layout and Bypassing TTL-/CMOS-Compatible Output Stage Using/Disabling the Latch Feature Optimizing Performance Comparator Propagation Delay Dispersion Comparator Hysteresis Crossover Bias Point Minimum Input Slew Rate Requirement Typical Application Circuits Outline Dimensions Ordering Guide