Datasheet ADP7157 (Analog Devices)

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1.2 A, Ultralow Noise, High PSRR, RF Linear Regulator Data Sheet ADP7157 FEATURES TYPICAL APPLICATION CIRCUIT Input voltage range: 2.3 V to 5.5 V Adjustable output voltage range (V ADP7157 OUT): 1.2 V to 3.3 V VIN = 3.8V VOUT = 3.3V Maximum load current: 1.2 A VIN VOUT C C IN OUT Low noise 10µF 10µF VOUT_SENSE ON 0.9 µV rms typical output noise from 100 Hz to 100 kHz EN REF C 1.6 µV rms typical output noise from 10 Hz to 100 kHz REF OFF 1µF R1 Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz BYP CBYP V Power supply rejection ratio (PSRR) 1µF REF_SENSE OUT = 1.2V × (R1 + R2)/R2 82 dB from 1 kHz to 100 kHz R2 VREG C 1kΩ < R2 < 200kΩ 55 dB at 1 MHz REG 1µF GND Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V
001
Initial accuracy: ±0.6% at I LOAD = 10 mA
12938-
Accuracy over line, load, and temperature: ±1.5%
Figure 1. Regulated 3.3 V Output from a 3.8 V Input
Operating supply current (IGND) 4.0 mA typical at 0 µA 7.0 mA typical at 1.2 A Low shutdown current: 0.2 μA typical Stable with a 10 µF ceramic output capacitor 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages Precision enable Table 1. Related Devices Supported by ADIsimPower t ool Input Output Fixed/ Model Voltage Current Adjustable Package APPLICATIONS
ADP7159, 2.3 V to 2 A Fixed 10-lead LFCSP/
Regulation to noise sensitive applications: phase-locked
ADP7158 5.5 V 8-lead SOIC
loops (PLLs), voltage controlled oscillators (VCOs), and
ADP7156 2.3 V to 1.2 A Fixed/ 10-lead LFCSP/
PLLs with integrated VCOs
5.5 V Adjustable 8-lead SOIC
Communications and infrastructure
ADM7150, 4.5 V to 800 mA Fixed/ 8-lead LFCSP/
Backhaul and microwave links
ADM7151 16 V Adjustable 8-lead SOIC ADM7154, 2.3 V to 600 mA Fixed/ 8-lead LFCSP/
GENERAL DESCRIPTION
ADM7155 5.5 V Adjustable 8-lead SOIC The ADP7157 is an adjustable linear regulator that operates ADM7160 2.2 V to 200 mA Fixed 6-lead LFCSP/ 5.5 V 5-lead TSOT from 2.3 V to 5.5 V and provides up to 1.2 A of output current.
1k
Output voltages from 1.2 V to 3.3 V are possible depending on
CBYP = 1µF CBYP = 10µF
the model. Using an advanced proprietary architecture, the
) CBYP = 100µF CBYP = 1000µF
device provides high power supply rejection and ultralow noise,
√Hz V/ 100
achieving excellent line and load transient response with only a
(n Y
10 µF ceramic output capacitor.
IT NS
The ADP7157 is available in four models that optimize power
DE 10 L A
dissipation and PSRR performance as a function of the input
R T
and output voltage. See Table 9 and Table 10 for selection guides. The typical output noise the ADP7157 regulator is 0.9 μV rms from
1 ISE SPEC
100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral density from
O N
10 kHz to 1 MHz. The ADP7157 is available in 10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages, making it not only a
0.110 100 1k 10k 100k 1M 10M
002 very compact solution, but also providing excellent thermal
FREQUENCY (Hz)
12939- performance for applications requiring up to 1.2 A of output Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V current in a small, low profile footprint.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input and VREG Capacitor REF Capacitor BYP Capacitor Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) PROGRAMMABLE PRECISION ENABLE START-UP TIME REF, BYP, AND VREG PINS CURRENT-LIMIT AND THERMAL SHUTDOWN THERMAL CONSIDERATIONS Thermal Characterization Parameter (ΨJB) PSRR PERFORMANCE PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE