Datasheet ADP5030 (Analog Devices)

FabricanteAnalog Devices
DescripciónDual, 200 mA, High Performance RF LDO with Load Switch
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RevisiónB
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Dual, 200 mA, High Performance. RF LDO with Load Switch. ADP5030. FEATURES. APPLICATIONS. Input voltage range: 2.5 V to 5.5 V

Datasheet ADP5030 Analog Devices, Revisión: B

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Dual, 200 mA, High Performance RF LDO with Load Switch ADP5030 FEATURES APPLICATIONS Input voltage range: 2.5 V to 5.5 V RF subsystems Dual, 200 mA low dropout voltage regulators GPS devices Tiny, 16-ball, 1.6 mm × 1.6 mm WLCSP GENERAL DESCRIPTION Initial accuracy: ±0.7% Stable with 1 μF ceramic output capacitors
The ADP5030 combines two high performance, low dropout
Overcurrent and thermal protection
(LDO) voltage regulators, a low RDSON load switch, and level
High PSRR
shifting logic in a tiny, 16-ball, 1.6 mm × 1.6 mm WLCSP to
76 dB up to 1 kHz
meet demanding performance and board space requirements.
70 dB at 10 kHz
The low quiescent current, low dropout voltage, and wide input
60 dB at 100 kHz
voltage range of the ADP5030 LDOs extend the battery life of
40 dB at 1 MHz
portable devices. The ADP5030 LDOs maintain power supply
Low output noise
rejection greater than 60 dB for frequencies as high as 100 kHz
27 μV rms typical output noise at VOUTx = 1.2 V
while operating with a low headroom voltage.
50 μV rms typical output noise at VOUTx = 2.8 V
The ADP5030 can be configured in two different activation
Excellent transient response
modes for LDO2 and the load switch; these modes are selected
Low dropout voltage: 175 mV at 200 mA load
by a dedicated pin (MSEL).
60 μA typical ground current at no load, both LDOs enabled Guaranteed 200 mA output current per regulator Load switch with low RDSON of 100 mΩ at 1.8 V High-to-low voltage and low-to-high voltage level shifting logic −40°C to +125°C junction temperature FUNCTIONAL BLOCK DIAGRAM POWER SUPPLY AND VIN3 PERIPHERAL VIN3 PROCESSOR ADP5030 MODULE VIN1 VOUT1 VDD LDO1 VBB C1 C2 1µF EN1 1µF VOUT2 GPO4_1V8 LDO2 VAUX MSEL C3 1µF V1_8DIG VIN2 LOAD VOUT3 VIO SWITCH C4 C5 0.1µF 2.2µF VIN2 EN2 GPO2_1V8 VIN3 GPOUT1 GPIN1 GPI0_1V8 GPO0_1V2 GPIN2 GPOUT2 GPO0_1V8 GPI0_1V2 VIN3 GPIN3 GPOUT3 GPO1_1V8 GPI1_1V2 1.8V INPUT/OUTPUT GND 1.2V INPUT/OUTPUT
01 0
SYSTEM
3-
SYSTEM
89 07 Figure 1.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION LDO2 AND LOAD SWITCH ACTIVATION LOGIC SEQUENCING CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PCB LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE