Datasheet ADSP-21065L-EP (Analog Devices) - 4
| Fabricante | Analog Devices |
| Descripción | SHARC DSP Microcomputer |
| Páginas / Página | 14 / 4 — ADSP-21065L-EP. Enhanced Product. GENERAL DESCRIPTION. Table 1. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 360 Kb |
| Idioma del documento | Inglés |
ADSP-21065L-EP. Enhanced Product. GENERAL DESCRIPTION. Table 1. Performance Benchmarks. Benchmark. Timing. Cycles
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ADSP-21065L-EP Enhanced Product GENERAL DESCRIPTION
The ADSP-21065L-EP is a powerful member of the SHARC®
Table 1. Performance Benchmarks
family of 32-bit processors optimized for cost sensitive applica- tions. The SHARC (Super Harvard Architecture) processors
Benchmark Timing Cycles
offer the highest levels of performance and memory integration Cycle Time 16.5 ns 1 of any 32-bit DSP in the industry—they are also the only DSPs 1024-Point Complex FFT in the industry that offer both fixed and floating-point capabili- (Radix 4, with Digit Reverse) 301 s 18,221 ties, without compromising precision or performance. Matrix Multiply (Pipelined) The ADSP-21065L-EP is fabricated in a high speed, low power [3 × 3] × [3 × 1] 148.5 ns 9 CMOS process, 0.35 μm technology. With its on-chip instruc- [4 × 4] × [4 × 1] 264 ns 16 tion cache, the processor can execute every instruction in a FIR Filter (per Tap) 16.5 ns 1 single cycle. Table 1 lists the performance benchmarks for the IIR Filter (per Biquad) 66 ns 4 ADSP-21065L-EP. Divide (y/x) 99 ns 6 The ADSP-21065L-EP SHARC combines a floating-point DSP Inverse Square Root 148.5 ns 9 core with integrated, on-chip system features, including a 544K bit SRAM memory, host processor interface, DMA con- DMA Transfers 240M bytes/s troller, SDRAM controller, and enhanced serial ports. Full details about this enhanced product are available in the Figure 1 shows a block diagram of the ADSP-21065L-EP, illus- ADSP-21065L data sheet, which should be used in conjunction trating the following architectural features: with this data sheet. • Computation units (ALU, multiplier, and shifter) with a shared data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • Timers with event capture modes • On-chip, dual-ported SRAM • External port for interfacing to off-chip memory and peripherals • Host port and SDRAM interface • DMA controller • Enhanced serial ports • JTAG test access port Rev. B | Page 4 of 14 | September 2017 Document Outline Summary Enhanced Product (EP) Features Features Table of Contents Revision History General Description Pin Function Descriptions Specifications Operating Conditions Absolute Maximum Ratings ESD Caution Package Marking Information Environmental Conditions Thermal Characteristics 208-LEAD MQFP Pin Configuration Outline Dimensions Ordering Guide
ADSP-21065L-EP Enhanced Product GENERAL DESCRIPTION
The ADSP-21065L-EP is a powerful member of the SHARC®
Table 1. Performance Benchmarks
family of 32-bit processors optimized for cost sensitive applica- tions. The SHARC (Super Harvard Architecture) processors
Benchmark Timing Cycles
offer the highest levels of performance and memory integration Cycle Time 16.5 ns 1 of any 32-bit DSP in the industry—they are also the only DSPs 1024-Point Complex FFT in the industry that offer both fixed and floating-point capabili- (Radix 4, with Digit Reverse) 301 s 18,221 ties, without compromising precision or performance. Matrix Multiply (Pipelined) The ADSP-21065L-EP is fabricated in a high speed, low power [3 × 3] × [3 × 1] 148.5 ns 9 CMOS process, 0.35 μm technology. With its on-chip instruc- [4 × 4] × [4 × 1] 264 ns 16 tion cache, the processor can execute every instruction in a FIR Filter (per Tap) 16.5 ns 1 single cycle. Table 1 lists the performance benchmarks for the IIR Filter (per Biquad) 66 ns 4 ADSP-21065L-EP. Divide (y/x) 99 ns 6 The ADSP-21065L-EP SHARC combines a floating-point DSP Inverse Square Root 148.5 ns 9 core with integrated, on-chip system features, including a 544K bit SRAM memory, host processor interface, DMA con- DMA Transfers 240M bytes/s troller, SDRAM controller, and enhanced serial ports. Full details about this enhanced product are available in the Figure 1 shows a block diagram of the ADSP-21065L-EP, illus- ADSP-21065L data sheet, which should be used in conjunction trating the following architectural features: with this data sheet. • Computation units (ALU, multiplier, and shifter) with a shared data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • Timers with event capture modes • On-chip, dual-ported SRAM • External port for interfacing to off-chip memory and peripherals • Host port and SDRAM interface • DMA controller • Enhanced serial ports • JTAG test access port Rev. B | Page 4 of 14 | September 2017 Document Outline Summary Enhanced Product (EP) Features Features Table of Contents Revision History General Description Pin Function Descriptions Specifications Operating Conditions Absolute Maximum Ratings ESD Caution Package Marking Information Environmental Conditions Thermal Characteristics 208-LEAD MQFP Pin Configuration Outline Dimensions Ordering Guide