Datasheet M29W040B (STMicroelectronics) - 6

M29W040B Table 5. Commands Bus Write Operations th Command ng 1st 2nd 3rd 4th 5th 6th Le Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1 X F0 Read/Reset 3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 PA PD Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass 2 X A0 PA PD Program Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Block Erase 6+ 555 AA 2AA 55 555 80 555 AA 2AA 55 BA 30 Erase Suspend 1 X B0 Erase Resume 1 X 30 Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses address bits A0-A10 to verify the commands, the upper address bits are Don’t Care.
Read/Reset.
After a Read/Reset command, read the memory as normal until another command is issued.
Auto Select.
After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.
Program, Unlock Bypass Program, Chip Erase, Block Erase.
After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional Bus Write Operations until the Timeout Bit is set.
Unlock Bypass.
After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.
Unlock Bypass Reset.
After the Unlock Bypass Reset command read the memory as normal until another command is issued.
Erase Suspend.
After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program commands on non-erasing blocks as normal.
Erase Resume.
After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Program/ Erase Controller completes and the memory returns to Read Mode.
Chip Erase Command.
The Chip Erase com- times are given in Table 6. All Bus Read opera- mand can be used to erase the entire chip. Six Bus tions during the Chip Erase operation will output Write operations are required to issue the Chip the Status Register on the Data Inputs/Outputs. Erase Command and start the Program/Erase See the section on the Status Register for more Controller. details. If any blocks are protected then these are ignored After the Chip Erase operation has completed the and all the other blocks are erased. If all of the memory will return to the Read Mode, unless an blocks are protected the Chip Erase operation ap- error has occurred. When an error occurs the pears to start but will terminate within about 100µs, memory will continue to output the Status Regis- leaving the data unchanged. No error condition is ter. A Read/Reset command must be issued to re- given when protected blocks are ignored. set the error condition and return to Read Mode. During the erase operation the memory will ignore The Chip Erase Command sets all of the bits in un- all commands. It is not possible to issue any com- protected blocks of the memory to ‘1’. All previous mand to abort the operation. Typical chip erase data is lost. 6/20 Document Outline Table 1. Signal Names Table 2. Absolute Maximum Ratings (1) Table 3. Uniform Block Addresses, M29W040B Table 4. Bus Operations Table 5. Commands Read/Reset. Auto Select. Program, Unlock Bypass Program, Chip Erase, Block Erase. Unlock Bypass. Unlock Bypass Reset. Erase Suspend. Erase Resume. Table 6. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70˚C or –40 to 85˚C) Table 7. Status Register Bits Table 8. AC Measurement Conditions Table 9. Capacitance (TA = 25 ˚C, f = 1 MHz) Table 10. DC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 11. Read AC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 14. Ordering Information Scheme Table 15. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Table 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data Table 18. Revision History SUMMARY DESCRIPTION SIGNAL DESCRIPTIONS Address Inputs (A0-A18). Data Inputs/Outputs (DQ0-DQ7). Chip Enable (E). Output Enable (G). Write Enable (W). VCC Supply Voltage. VSS Ground. BUS OPERATIONS Bus Read. Bus Write. Output Disable. Standby. Automatic Standby. Special Bus Operations Electronic Signature. Block Protection and Blocks Unprotection. COMMAND INTERFACE Read/Reset Command. Auto Select Command. Program Command. Unlock Bypass Command. Unlock Bypass Program Command. Unlock Bypass Reset Command. Chip Erase Command. Block Erase Command. Erase Suspend Command. Erase Resume Command. STATUS REGISTER Data Polling Bit (DQ7). Toggle Bit (DQ6). Error Bit (DQ5). Erase Timer Bit (DQ3). Alternative Toggle Bit (DQ2). Figure 1. Logic Diagram Figure 2. PLCC Connections Figure 3. TSOP Connections Figure 4. Data Polling Flowchart Figure 5. Data Toggle Flowchart Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit Figure 8. Read Mode AC Waveforms Figure 9. Write AC Waveforms, Write Enable Controlled Figure 10. Write AC Waveforms, Chip Enable Controlled Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline Figure 13. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline