Datasheet LTC6228, LTC6229 (Analog Devices) - 17
| Fabricante | Analog Devices |
| Descripción | 0.88nV/√Hz 730MHz, 500V/µs, Low Distortion Rail-to-Rail Output Op Amps with Shutdown |
| Páginas / Página | 30 / 17 — APPLICATIONS INFORMATION Circuit Description. Input Bias Current. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 2.6 Mb |
| Idioma del documento | Inglés |
APPLICATIONS INFORMATION Circuit Description. Input Bias Current. Figure 1. LTC6228 Simplified Schematic Diagram
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APPLICATIONS INFORMATION Circuit Description
supplies via M2 and M1), and disable_bias, which disables The LTC6228/LTC6229 have an input signal range that the input bias cancellation circuit, by shorting the base of extends from the negative power supply to 1.2V below Q19 to V– through M3. the positive power supply. Figure 1 depicts a simplified schematic of the amplifier. The input stage consists of
Input Bias Current
PNP transistors Q1 and Q2. At the input stage, devices The LTC6228 family has an input bias current of approxi- Q18 and Q19 act to cancel the bias current of the input mately 16μA. For the LTC6228 and the LTC6229DD10, pair when bias cancellation is enabled. Bootstrap transistor the input bias current can be reduced to under 2.5μA at Q13 and R5 match the collector and emitter voltages of room temperature when the SHDN pin voltage is taken to Q11 and Q12, thus enhancing gain by improving output within 350mV of the positive power supply. This capabil- impedance. By making the collector current of Q13 twice ity enables the input bias current cancellation circuitry, that of Q11 and Q12, the base currents of Q11 and Q12 allowing the amplifiers to be used in DC applications do not contribute towards mismatch between the collec- involving source impedances. tor currents of Q9 and Q8. This improves DC accuracy. A pair of complementary common emitter stages, Q15 and When input bias current cancellation is enabled and the Q14, enables the output to swing to either rail. The SHDN input common mode voltage is within approximately Interface block translates the SHDN signal into 2 signals, 500mV of V–, the bias cancellation is no longer effec- pwr_dn for powering down the device (by deactivating tive, because transistors Q18 and Q19 in Figure 1 enter current sources I1 - I4) and putting the output in a high saturation. The input bias current can then exceed 50μA impedance state (by shorting the bases of Q15/Q14 to the or higher, which is more than the input bias current V+ pwr_dn I3 pwr_dn M2 + Q15 V+ V– + R3 R4 R5 pwr_dn I2 pwr_dn I1 C2 ESDD5 ESDD1 ESDD2 Q12 Q11 Q13 +IN pwr_dn V– CC SHDN D5 D7 SHDN Q1 Q2 INTERFACE OUT BLOCK V+ –IN disable_bias pwr_dn ESDD4 ESDD3 I4 BUFFER AND Q16 OUTPUT BIAS V– V+ Q9 Q8 ESDD6 Q10 Q17 Q18 Q19 pwr_dn M1 C1 disable_bias M3 R1 R2 R3 Q14 V– 6228 F01
Figure 1. LTC6228 Simplified Schematic Diagram
Rev. B For more information www.analog.com 17 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics (VS = ±5V) Electrical Characteristics (VS = 5V, 0V) Electrical Characteristics (VS = 3V, 0V) Typical Performance Characteristics Pin Functions Applications Information Typical Applications Package Description Revision History Typical Application Related Parts
APPLICATIONS INFORMATION Circuit Description
supplies via M2 and M1), and disable_bias, which disables The LTC6228/LTC6229 have an input signal range that the input bias cancellation circuit, by shorting the base of extends from the negative power supply to 1.2V below Q19 to V– through M3. the positive power supply. Figure 1 depicts a simplified schematic of the amplifier. The input stage consists of
Input Bias Current
PNP transistors Q1 and Q2. At the input stage, devices The LTC6228 family has an input bias current of approxi- Q18 and Q19 act to cancel the bias current of the input mately 16μA. For the LTC6228 and the LTC6229DD10, pair when bias cancellation is enabled. Bootstrap transistor the input bias current can be reduced to under 2.5μA at Q13 and R5 match the collector and emitter voltages of room temperature when the SHDN pin voltage is taken to Q11 and Q12, thus enhancing gain by improving output within 350mV of the positive power supply. This capabil- impedance. By making the collector current of Q13 twice ity enables the input bias current cancellation circuitry, that of Q11 and Q12, the base currents of Q11 and Q12 allowing the amplifiers to be used in DC applications do not contribute towards mismatch between the collec- involving source impedances. tor currents of Q9 and Q8. This improves DC accuracy. A pair of complementary common emitter stages, Q15 and When input bias current cancellation is enabled and the Q14, enables the output to swing to either rail. The SHDN input common mode voltage is within approximately Interface block translates the SHDN signal into 2 signals, 500mV of V–, the bias cancellation is no longer effec- pwr_dn for powering down the device (by deactivating tive, because transistors Q18 and Q19 in Figure 1 enter current sources I1 - I4) and putting the output in a high saturation. The input bias current can then exceed 50μA impedance state (by shorting the bases of Q15/Q14 to the or higher, which is more than the input bias current V+ pwr_dn I3 pwr_dn M2 + Q15 V+ V– + R3 R4 R5 pwr_dn I2 pwr_dn I1 C2 ESDD5 ESDD1 ESDD2 Q12 Q11 Q13 +IN pwr_dn V– CC SHDN D5 D7 SHDN Q1 Q2 INTERFACE OUT BLOCK V+ –IN disable_bias pwr_dn ESDD4 ESDD3 I4 BUFFER AND Q16 OUTPUT BIAS V– V+ Q9 Q8 ESDD6 Q10 Q17 Q18 Q19 pwr_dn M1 C1 disable_bias M3 R1 R2 R3 Q14 V– 6228 F01
Figure 1. LTC6228 Simplified Schematic Diagram
Rev. B For more information www.analog.com 17 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics (VS = ±5V) Electrical Characteristics (VS = 5V, 0V) Electrical Characteristics (VS = 3V, 0V) Typical Performance Characteristics Pin Functions Applications Information Typical Applications Package Description Revision History Typical Application Related Parts