Datasheet ADP1853 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Synchronous, Step-Down DC-to-DC Controller with Voltage Tracking and Synchronization |
| Páginas / Página | 28 / 9 — Data Sheet. ADP1853. Pin No. Mnemonic. Description |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
Data Sheet. ADP1853. Pin No. Mnemonic. Description
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Data Sheet ADP1853 Pin No. Mnemonic Description
17 PGOOD Power Good. The open-drain power good indicator logic output with an internal 12.5 kΩ resistor is connected between PGOOD and VCCO. PGOOD is pulled to ground when the output is outside the regulation window. An external pull-up resistor is not required. If the controller is configured as a slave in the interleaved dual-phase application by tying the FB pin high to VCCO, the pulse skip mode is enabled by driving the PGOOD pin low externally in cases when the master is in pulse skip mode at light loads. Otherwise, if the master is configured to forced PWM operation, PGOOD of the slave controller must be connected to the PGOOD of the master. 18 RAMP Programmable Current Setting for Slope Compensation. Connect a resistor from RAMP to VIN. The voltage at RAMP is 0.2 V during operation. This pin is high impedance when the channel is disabled. 19 FREQ Internal Oscillator Frequency, fOSC. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz or tie FREQ to VCCO for 600 kHz operating frequency.
20 TRK Tracking Input. Connect TRK to VCCO if tracking is not used. EPAD Exposed Pad. Connect the bottom of the exposed pad to the system AGND plane. Rev. A | Page 9 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONTROL ARCHITECTURE OSCILLATOR FREQUENCY SYNCHRONIZATION PWM OR PULSE SKIP MODE OF OPERATION CLKOUT SIGNAL SYNCHRONOUS RECTIFIER AND DEAD TIME INPUT UNDERVOLTAGE LOCKOUT INTERNAL LINEAR REGULATOR OVERVOLAGE PROTECTION POWER GOOD SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION ENABLE/DISABLE CONTROL THERMAL OVERLOAD PROTECTION INTERLEAVED DUAL-PHASE OPERATION APPLICATIONS INFORMATION ADISIMPOWER DESIGN TOOL SETTING THE OUTPUT VOLTAGE SOFT START SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING INPUT CAPACITOR SELECTION VIN PIN FILTER BOOST CAPACITOR SELECTION INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION MOSFET SELECTION LOOP COMPENSATION—VOLTAGE MODE Type III Compensation LOOP COMPENSATION—CURRENT MODE Setting the Slope Compensation Setting the Current Sense Gain Type II Compensation SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING Coincident Tracking Ratiometric Tracking PCB LAYOUT GUIDLINES TYPICAL OPERATING CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE
17 PGOOD Power Good. The open-drain power good indicator logic output with an internal 12.5 kΩ resistor is connected between PGOOD and VCCO. PGOOD is pulled to ground when the output is outside the regulation window. An external pull-up resistor is not required. If the controller is configured as a slave in the interleaved dual-phase application by tying the FB pin high to VCCO, the pulse skip mode is enabled by driving the PGOOD pin low externally in cases when the master is in pulse skip mode at light loads. Otherwise, if the master is configured to forced PWM operation, PGOOD of the slave controller must be connected to the PGOOD of the master. 18 RAMP Programmable Current Setting for Slope Compensation. Connect a resistor from RAMP to VIN. The voltage at RAMP is 0.2 V during operation. This pin is high impedance when the channel is disabled. 19 FREQ Internal Oscillator Frequency, fOSC. Sets the desired operating frequency between 200 kHz and 1.5 MHz with one resistor between FREQ and AGND. Connect FREQ to AGND for a preprogrammed 300 kHz or tie FREQ to VCCO for 600 kHz operating frequency.
20 TRK Tracking Input. Connect TRK to VCCO if tracking is not used. EPAD Exposed Pad. Connect the bottom of the exposed pad to the system AGND plane. Rev. A | Page 9 of 28 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION SIMPLIFIED BLOCK DIAGRAM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CONTROL ARCHITECTURE OSCILLATOR FREQUENCY SYNCHRONIZATION PWM OR PULSE SKIP MODE OF OPERATION CLKOUT SIGNAL SYNCHRONOUS RECTIFIER AND DEAD TIME INPUT UNDERVOLTAGE LOCKOUT INTERNAL LINEAR REGULATOR OVERVOLAGE PROTECTION POWER GOOD SHORT-CIRCUIT AND CURRENT-LIMIT PROTECTION ENABLE/DISABLE CONTROL THERMAL OVERLOAD PROTECTION INTERLEAVED DUAL-PHASE OPERATION APPLICATIONS INFORMATION ADISIMPOWER DESIGN TOOL SETTING THE OUTPUT VOLTAGE SOFT START SETTING THE CURRENT LIMIT ACCURATE CURRENT-LIMIT SENSING INPUT CAPACITOR SELECTION VIN PIN FILTER BOOST CAPACITOR SELECTION INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION MOSFET SELECTION LOOP COMPENSATION—VOLTAGE MODE Type III Compensation LOOP COMPENSATION—CURRENT MODE Setting the Slope Compensation Setting the Current Sense Gain Type II Compensation SWITCHING NOISE AND OVERSHOOT REDUCTION VOLTAGE TRACKING Coincident Tracking Ratiometric Tracking PCB LAYOUT GUIDLINES TYPICAL OPERATING CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE