Datasheet HT12D, HT12F (Holtek) - 2
| Fabricante | Holtek |
| Descripción | 212 Series of Decoders |
| Páginas / Página | 12 / 2 — HT12D/HT12F. Block Diagram. Pin Assignment. 8 - A d d r e s s. 1 2 - A d … |
| Formato / tamaño de archivo | PDF / 115 Kb |
| Idioma del documento | Inglés |
HT12D/HT12F. Block Diagram. Pin Assignment. 8 - A d d r e s s. 1 2 - A d d r e s s. 4 - D a t a. 0 - D a t a. H T 1 2 D. H T 1 2 F
Línea de modelo para esta hoja de datos
Versión de texto del documento
HT12D/HT12F Block Diagram
O S C 2 O S C 1 O s c i l a t o r D i v i d e r D a t a S h i f t R e g i s t e r L a t c h C i r c u i t D a t a D I N B u f f e r D a t a D e t e c t o r S y n c . D e t e c t o r C o m p a r a t o r C o m p a r a t o r C o n t r o l L o g i c T r a n s m i s s i o n G a t e C i r c u i t B u f f e r V T A d d r e s s V D D V S S Note: The address/data pins are available in various combinations (see the address/data table).
Pin Assignment 8 - A d d r e s s 8 - A d d r e s s 1 2 - A d d r e s s 1 2 - A d d r e s s 4 - D a t a 4 - D a t a 0 - D a t a 0 - D a t a
N C 1 2 0 N C N C 1 2 0 N C A 0 1 1 8 V D D A 0 2 1 9 V D D A 0 1 1 8 V D D A 0 2 1 9 V D D A 1 2 1 7 V T A 1 3 1 8 V T A 1 2 1 7 V T A 1 3 1 8 V T A 2 3 1 6 O S C 1 A 2 4 1 7 O S C 1 A 2 3 1 6 O S C 1 A 2 4 1 7 O S C 1 A 3 4 1 5 O S C 2 A 3 5 1 6 O S C 2 A 3 4 1 5 O S C 2 A 3 5 1 6 O S C 2 A 4 5 1 4 D I N A 4 6 1 5 D I N A 4 5 1 4 D I N A 4 6 1 5 D I N A 5 6 1 3 D 1 1 A 5 7 1 4 D 1 1 A 5 6 1 3 A 1 1 A 5 7 1 4 A 1 1 A 6 7 1 2 D 1 0 A 6 8 1 3 D 1 0 A 6 7 1 2 A 1 0 A 6 8 1 3 A 1 0 A 7 8 1 1 D 9 A 7 9 1 2 D 9 A 7 8 1 1 A 9 A 7 9 1 2 A 9 V S S 9 1 0 D 8 V S S 1 0 1 1 D 8 V S S 9 1 0 A 8 V S S 1 0 1 1 A 8
H T 1 2 D H T 1 2 D H T 1 2 F H T 1 2 F 1 8 D I P - A 2 0 S O P - A 1 8 D I P - A 2 0 S O P - A Pin Description Internal Pin Name I/O Description Connection
Input pins for address A0~A11 setting A0~A11 (HT12F) NMOS These pins can be externally set to VSS or left open. I Transmission Gate Input pins for address A0~A7 setting A0~A7 (HT12D) These pins can be externally set to VSS or left open. D8~D11 (HT12D) O CMOS OUT Output data pins, power-on state is low. DIN I CMOS IN Serial data input pin VT O CMOS OUT Valid transmission, active high OSC1 I Oscillator Oscillator input pin OSC2 O Oscillator Oscillator output pin VSS ¾ ¾ Negative power supply, ground VDD ¾ ¾ Positive power supply Rev. 1.20 2 February 20, 2009 Document Outline Features Applications General Description Selection Table Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings Electrical Characteristics Functional Description Application Circuits Package Information Product Tape and Reel Specifications
O S C 2 O S C 1 O s c i l a t o r D i v i d e r D a t a S h i f t R e g i s t e r L a t c h C i r c u i t D a t a D I N B u f f e r D a t a D e t e c t o r S y n c . D e t e c t o r C o m p a r a t o r C o m p a r a t o r C o n t r o l L o g i c T r a n s m i s s i o n G a t e C i r c u i t B u f f e r V T A d d r e s s V D D V S S Note: The address/data pins are available in various combinations (see the address/data table).
Pin Assignment 8 - A d d r e s s 8 - A d d r e s s 1 2 - A d d r e s s 1 2 - A d d r e s s 4 - D a t a 4 - D a t a 0 - D a t a 0 - D a t a
N C 1 2 0 N C N C 1 2 0 N C A 0 1 1 8 V D D A 0 2 1 9 V D D A 0 1 1 8 V D D A 0 2 1 9 V D D A 1 2 1 7 V T A 1 3 1 8 V T A 1 2 1 7 V T A 1 3 1 8 V T A 2 3 1 6 O S C 1 A 2 4 1 7 O S C 1 A 2 3 1 6 O S C 1 A 2 4 1 7 O S C 1 A 3 4 1 5 O S C 2 A 3 5 1 6 O S C 2 A 3 4 1 5 O S C 2 A 3 5 1 6 O S C 2 A 4 5 1 4 D I N A 4 6 1 5 D I N A 4 5 1 4 D I N A 4 6 1 5 D I N A 5 6 1 3 D 1 1 A 5 7 1 4 D 1 1 A 5 6 1 3 A 1 1 A 5 7 1 4 A 1 1 A 6 7 1 2 D 1 0 A 6 8 1 3 D 1 0 A 6 7 1 2 A 1 0 A 6 8 1 3 A 1 0 A 7 8 1 1 D 9 A 7 9 1 2 D 9 A 7 8 1 1 A 9 A 7 9 1 2 A 9 V S S 9 1 0 D 8 V S S 1 0 1 1 D 8 V S S 9 1 0 A 8 V S S 1 0 1 1 A 8
H T 1 2 D H T 1 2 D H T 1 2 F H T 1 2 F 1 8 D I P - A 2 0 S O P - A 1 8 D I P - A 2 0 S O P - A Pin Description Internal Pin Name I/O Description Connection
Input pins for address A0~A11 setting A0~A11 (HT12F) NMOS These pins can be externally set to VSS or left open. I Transmission Gate Input pins for address A0~A7 setting A0~A7 (HT12D) These pins can be externally set to VSS or left open. D8~D11 (HT12D) O CMOS OUT Output data pins, power-on state is low. DIN I CMOS IN Serial data input pin VT O CMOS OUT Valid transmission, active high OSC1 I Oscillator Oscillator input pin OSC2 O Oscillator Oscillator output pin VSS ¾ ¾ Negative power supply, ground VDD ¾ ¾ Positive power supply Rev. 1.20 2 February 20, 2009 Document Outline Features Applications General Description Selection Table Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings Electrical Characteristics Functional Description Application Circuits Package Information Product Tape and Reel Specifications