Datasheet TB9053FTG,TB9054FTG - Preliminary (Toshiba) - 8
| Fabricante | Toshiba |
| Descripción | Bi-CMOS Linear Integrated Circuit, Silicon Monolithic |
| Páginas / Página | 36 / 8 — Preliminary. Table 5.5 DIAG function (Combined 2-channel mode) |
| Formato / tamaño de archivo | PDF / 2.2 Mb |
| Idioma del documento | Inglés |
Preliminary. Table 5.5 DIAG function (Combined 2-channel mode)
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Preliminary
TB9053FTG,TB9054FTG Motor drive output Is EN/ENB pulse input Function EN1 ENB1 EN2 ENB2 DIAG1 DIAG2 needed when DIAG pin pin OUT1 OUT2 OUT3 OUT4 is cleared? When initial/restarted diagnosis is attempted but it does not start (Detection of Ch1 over-current or X X X X No L H/L Hiz Hiz *1 *1 open load during operation/non- operation) When initial/restarted diagnosis is attempted but it does not start (Detection of Ch2 over-current or X X X X No H/L L *1 *1 Hiz Hiz open load during operation/non- operation) When SPI communication disruption is detected X X X X No L L *2 *2 *2 *2 When an SPI communication CRC error is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz When a fault SPI communication SCLK clock count is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz When a fault SPI communication address is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz *1: Operation similar to Table 5.1 H-bridge motor function 1 *2: Operation specified in CONFIG1 DATA[8 ]
Table 5.5 DIAG function (Combined 2-channel mode)
Motor drive output Is EN/ENB pulse input Function EN1 ENB1 EN2 ENB2 DIAG1 DIAG2 needed when DIAG pin pin OUT1 OUT2 OUT3 OUT4 is cleared? Forward (Normal operation) H L H L - H H H H L L Reverse (Normal operation) H L H L - H H L L H H Short brake (Normal operation) H L H L - H H L/H L/H L/H L/H EN1 and EN2 Disable L X L X No L L Hiz Hiz Hiz Hiz ENB1 and ENB2 Disable X H X H No L L Hiz Hiz Hiz Hiz Sleep mode X L/H X L/H - H H Hiz Hiz Hiz Hiz When over-temperature is detected (TSD) X X X X No L L Hiz Hiz Hiz Hiz When Ch1 over-current is detected (ISD) X X X X Yes L H Hiz Hiz Hiz Hiz When Ch2 over-current is detected (ISD) X X X X Yes H L Hiz Hiz Hiz Hiz When VBAT under-voltage is detected X X X X No L L Hiz Hiz Hiz Hiz When VCC under-voltage is detected X X X X No L L Hiz Hiz Hiz Hiz When VCC under-voltage is detected (POR) X X X X No L L Hiz Hiz Hiz Hiz When Ch1-Ch2 open load during operation is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz When Ch1-Ch2 open load during non-operation is detected H L H L No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz © 20 20 8 2020-12-10 Toshiba Electronic Devices & Storage Corporation
Preliminary
TB9053FTG,TB9054FTG Motor drive output Is EN/ENB pulse input Function EN1 ENB1 EN2 ENB2 DIAG1 DIAG2 needed when DIAG pin pin OUT1 OUT2 OUT3 OUT4 is cleared? When initial/restarted diagnosis is attempted but it does not start (Detection of Ch1 over-current or X X X X No L H/L Hiz Hiz *1 *1 open load during operation/non- operation) When initial/restarted diagnosis is attempted but it does not start (Detection of Ch2 over-current or X X X X No H/L L *1 *1 Hiz Hiz open load during operation/non- operation) When SPI communication disruption is detected X X X X No L L *2 *2 *2 *2 When an SPI communication CRC error is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz When a fault SPI communication SCLK clock count is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz When a fault SPI communication address is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz *1: Operation similar to Table 5.1 H-bridge motor function 1 *2: Operation specified in CONFIG1 DATA[8 ]
Table 5.5 DIAG function (Combined 2-channel mode)
Motor drive output Is EN/ENB pulse input Function EN1 ENB1 EN2 ENB2 DIAG1 DIAG2 needed when DIAG pin pin OUT1 OUT2 OUT3 OUT4 is cleared? Forward (Normal operation) H L H L - H H H H L L Reverse (Normal operation) H L H L - H H L L H H Short brake (Normal operation) H L H L - H H L/H L/H L/H L/H EN1 and EN2 Disable L X L X No L L Hiz Hiz Hiz Hiz ENB1 and ENB2 Disable X H X H No L L Hiz Hiz Hiz Hiz Sleep mode X L/H X L/H - H H Hiz Hiz Hiz Hiz When over-temperature is detected (TSD) X X X X No L L Hiz Hiz Hiz Hiz When Ch1 over-current is detected (ISD) X X X X Yes L H Hiz Hiz Hiz Hiz When Ch2 over-current is detected (ISD) X X X X Yes H L Hiz Hiz Hiz Hiz When VBAT under-voltage is detected X X X X No L L Hiz Hiz Hiz Hiz When VCC under-voltage is detected X X X X No L L Hiz Hiz Hiz Hiz When VCC under-voltage is detected (POR) X X X X No L L Hiz Hiz Hiz Hiz When Ch1-Ch2 open load during operation is detected X X X X No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz When Ch1-Ch2 open load during non-operation is detected H L H L No L L H/L/Hiz H/L/Hiz H/L/Hiz H/L/Hiz © 20 20 8 2020-12-10 Toshiba Electronic Devices & Storage Corporation