Datasheet AD823 (Analog Devices) - 13

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Data Sheet AD823 THEORY OF OPERATION
The AD823 is fabricated on the Analog Devices, Inc. proprietary A nested integrator topology is used in the AD823 (see Figure 37). complementary bipolar (CB) process that enables the construction The output stage can be modeled as an ideal op amp with a of PNP and NPN transistors with similar fT’s in the 600 MHz to single-pole response and a unity-gain frequency set by 800 MHz region. In addition, the process also features N-Channel transconductance gm2 and Capacitor C2. R1 is the output JFETs that are used in the input stage of the AD823. These impedance of the input stage; gm is the input transconductance. process features allow the construction of high frequency, low C1 and C5 provide Miller compensation for the overall op amp. distortion op amps with picoamp input currents. This design The unity-gain frequency occurs at gm/C5. Solving the node uses a differential output input stage to maximize bandwidth equations for this circuit yields and headroom (see Figure 36). The smaller signal swings V OUT A0 required on the S1P/S1N outputs reduce the effect of the = Vi   C2   nonlinear currents due to junction capacitances and improve (sR [1 ( C1 A2 + ) 1 ] + ) 1 × s +    1 the distortion performance. With this design, harmonic   gm2   distortion of better than −91 dB @ 20 kHz into 600 Ω with where: VOUT = 4 V p-p on a single 5 V supply is achieved. The A0 = gmgm2 R2R1 (open-loop gain of op amp). complementary common emitter design of the output stage A2 = gm2 R2 (open-loop gain of output stage). provides excellent load drive without the need for emitter followers, thereby improving the output range of the device The first pole in the denominator is the dominant pole of the considerably with respect to conventional op amps. The amplifier and occurs at ~18 Hz. This equals the input stage AD823 can drive 20 mA with the outputs within 0.6 V of the output impedance R1 multiplied by the Miller-multiplied value supply rails. The AD823 also offers outstanding precision for a of C1. The second pole occurs at the unity-gain bandwidth of high speed op amp. Input offset voltages of 1 mV maximum the output stage, which is 23 MHz. This type of architecture and offset drift of 2 µV/°C are achieved through the use of the allows more open-loop gain and output drive to be obtained Analog Devices advanced thin film trimming techniques. than a standard 2-stage architecture would allow.
VCC Q44 R42 R37 Q43 Q55 V I6 A = 1 BE + 0.3V V1 I5 Q57 A = 19 Q61 Q49 Q58 Q72 Q18 C2 J1 J6 Q46 VINP R44 R28 Q54 V Q21 OUT VINN S1P S1N Q62 Q60 VCC C1 Q48 VB Q53 Q35 Q17 A = 19 I1 C6 R33 I2 R43 Q59 I3 Q56 I4 Q52 A = 1
036
VEE
00901- Figure 36. Simplified Schematic Rev. E | Page 13 of 20 Document Outline Features Applications Connection Diagram General Description Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Typical Performance Characteristics Theory of Operation Output Impedance Application Notes Input Characteristics Output Characteristics A/D Driver 3 V, Single-Supply Stereo Headphone Driver Second-Order Low-Pass Filter Single-Supply Half-Wave and Full-Wave Rectifiers Outline Dimensions Ordering Guide