Datasheet HMC8205BF10 (Analog Devices) - 11

Data Sheet HMC8205BF10 THEORY OF OPERATION
The HMC8205BF10 is a 35 W, GaN power amplifier consisting When biased as previously described, the device operates in of two cascaded gain stages. The first stage requires only a single Class A/B, resulting in maximum PAE at saturation. The positive drain supply, which also internally generates gate bias HMC8205BF10 features integrated RF chokes for each drain such that a first stage quiescent drain current of approximately plus on-chip dc blocking of the RFIN and RFOUT ports. 400 mA results for a 50 V drain voltage. The second stage has a Capacitive bypassing of the bias supplies improves performance distributed architecture that is biased by a separate positive and reduces the required external component count. drain supply plus an externally applied negative gate supply. The HMC8205BF10 is not rated for moisture sensitivity level. It When 50 V is used to bias the first and second stage drains is a nonhermetic, air cavity device, not surface mountable or together, adjust the negative voltage applied to VGG1 to obtain a suitable for use in a solder reflow process. The package body total quiescent drain current of 1300 mA. material is Tungsten Copper 85/15. Rev. C | Page 11 of 14 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Interface Schematics Typical Performance Characteristics Theory of Operation Applications Information Application Circuit Evaluation PCB Outline Dimensions Ordering Guide