Datasheet AD5560 (Analog Devices) - 58

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AD5560 Data Sheet READBACK MODE DAC READBACK
The AD5560 allows data readback via the serial interface from The DAC x1, DAC m, and DAC c registers are available to read every register directly accessible to the serial interface, which is back via the serial interface. Access to the calibrated x2 register al registers except the DAC register (x2 calibrated register). To is not available. read back contents of a register, it is necessary to write a 1 to
POWER-ON DEFAULT
the R/W bit, address the appropriate register, and fil the data bits with al zeros. During power-on, the power-on state machine resets all internal registers to their default values, and BUSY goes low. A rising After the write command has been written, data from the edge on BUSY indicates that the power-on event is complete selected register is loaded to the internal shift register and is and that the interface is enabled. The RESET pin has no available on the SDO pin during the next SPI operation. function in the power-on event. Address 0x43 and Address 0x44 are the only registers that are read only. The read function gives the user details of the alarm During power-on, all DAC x1 registers corresponding to 0 V status and the comparator output result. are cleared; the calibration register default corresponds to m at full scale and to c at zero scale. Alarm flags on latched alarm pins (Pin 1, Pin 2, Pin 3) and bits are cleared after a read command of Register 0x44 (alarm status The default conditions of the DPS and the system control and clear alarm register (see Table 25)). registers are as shown in the relevant tables (see Table 17 through Table 26). SCLK frequency for readback does not operate at the ful speed of the SPI interface. See the Timing Characteristics section for During a RESET function, al registers are reset to the power-on further details. default. Rev. E | Page 58 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE