Datasheet ADP5014 (Analog Devices) - 34

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ADP5014 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 6.10 0.30 6.00 SQ 0.23 PIN 1 INDICATOR 5.90 0.18 AREA P IN 1 31 40 IN D IC AT O R AR E A OP T IO N S 30 1 (SEE DETAIL A) 0.50 BSC 4.45 EXPOSED 4.30 SQ PAD 4.25 21 10 0.45 20 11 TOP VIEW BOTTOM VIEW 0.20 MIN 0.40 0.35 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO SIDE VIEW 0.75 THE PIN CONFIGURATION AND 0.05 MAX FUNCTION DESCRIPTIONS 0.70 0.02 NOM SECTION OF THIS DATA SHEET. COPLANARITY 0.08 SEATING PLANE 0.20 REF A 2018- -003438 08- G K P COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5 10-
Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP] 6 mm × 6 mm Body, and 0.75 mm Package Height (CP-40-10) Dimensions shown in millimeters
ORDERING GUIDE Model1 Temperature Range Package Description Package Option2
ADP5014ACPZ-R7 −40°C to +125°C 40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-10 ADP5014-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. 2 Table 13 lists the factory default options for the device. For a list of factory programmable options, see the Factory Programmable Options section. To order a device with options other than the default values, contact your local Analog Devices sales or distribution representative.
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Rev. A | Page 34 of 34 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK LOW NOISE OUTPUT DESIGN PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE