Datasheet A6275 (Allegro) - 2

FabricanteAllegro
Descripción8-Bit Serial Input Constant-Current Latched LED Driver
Páginas / Página12 / 2 — A6275. 8-Bit Serial Input Constant-Current Latched LED Driver. Features …
Formato / tamaño de archivoPDF / 363 Kb
Idioma del documentoInglés

A6275. 8-Bit Serial Input Constant-Current Latched LED Driver. Features and Benefits. Description. Packages

A6275 8-Bit Serial Input Constant-Current Latched LED Driver Features and Benefits Description Packages

Línea de modelo para esta hoja de datos

Versión de texto del documento

A6275 8-Bit Serial Input Constant-Current Latched LED Driver Features and Benefits Description
▪ Up to 90 mA constant-current outputs The A6275 is specifically designed for LED display applications. ▪ Undervoltage lockout Each BiCMOS device includes an 8-bit CMOS shift register, ▪ Low-power CMOS logic and latches accompanying data latches, and eight NPN constant-current ▪ High data-input rate sink drivers. ▪ Pin-compatible with TB62705CP The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. With a 5 V logic supply, typical serial data-input rates are up to 20 MHz. The LED drive current is de ter mined by the user selection of a single resistor. A CMOS serial data output permits cascade connections in applications requiring additional drive lines. For inter-digit
Packages
blanking, all output drivers can be disabled with an ENABLE input high. A similar 150 mA output device is available as the A6277; a similar 16-bit device is available as the A6276. Two package styles are provided: a through-hole DIP (suffix A) and a surface-mount SOICW (suffix LW). Under normal 16-pin DIP applications, copper leadframes and low logic-power dissipation (A package) allow these devices to sink maximum rated current through all outputs continuously over the operating temperature range (90 mA, 0.9 V drop, 85°C). Both packages are lead (Pb) free, with 100% matte tin leadframe plating. 16-pin SOICW Not to scale (LW package)
Functional Block Diagram
VDD LOGIC UVLO CLOCK SUPPLY SERIAL SERIAL SERIAL-PARALLEL SHIFT REGISTER DATA IN DATA OUT LATCH LATCHES ENABLE OUTPUT ENABLE GROUND (ACTIVE LOW) MOS BIPOLAR R I O EXT REGULATOR OUT 0 OUT 1 OUT 2 OUT N Dwg. FP-013-3
26185.200F