Datasheet SiC450, SiC451, SiC453 (Vishay) - 44
| Fabricante | Vishay |
| Descripción | 4.5 V to 20 V Input, 15 A, 25 A, 40 A microBuck DC/DC Converter With PMBus Interface |
| Páginas / Página | 48 / 44 — SiC450, SiC451, SiC453. PCB LAYOUT RECOMMENDATIONS Step 1: VIN/GND Planes … |
| Formato / tamaño de archivo | PDF / 1.3 Mb |
| Idioma del documento | Inglés |
SiC450, SiC451, SiC453. PCB LAYOUT RECOMMENDATIONS Step 1: VIN/GND Planes and Decoupling. Step 3: VSWH Plane. Fig. 62. Fig. 64
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SiC450, SiC451, SiC453
www.vishay.com Vishay Siliconix
PCB LAYOUT RECOMMENDATIONS Step 1: VIN/GND Planes and Decoupling Step 3: VSWH Plane
V plane IN VIN P plane GND nubber S VSWH P plane GND VSWH
Fig. 62
1. Layout VIN and PGND planes as shown above 2. Ceramic capacitors should be placed right between VIN and PGND, and very close to the device for best decoupling effect 3. Difference values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210 and 0603 4. Smaller capacitance value, closer to device VIN pin(s) - better high frequency noise absorbing
Fig. 64
1. Connect output inductor to SiC45x with large plane to
Step 2: V
lower the resistance
IN Pin
2. If any snubber network is required, place the components on the bottom side as shown above A plane GND V decouple cap IN
Fig. 63
1. VIN (pin 23) is the input pin for both internal LDO and tON block. tON time varies based on input voltage. It is necessary to put a decouple cap close to this pin S21-0213-Rev. B, 08-Mar-2021
44
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
www.vishay.com Vishay Siliconix
PCB LAYOUT RECOMMENDATIONS Step 1: VIN/GND Planes and Decoupling Step 3: VSWH Plane
V plane IN VIN P plane GND nubber S VSWH P plane GND VSWH
Fig. 62
1. Layout VIN and PGND planes as shown above 2. Ceramic capacitors should be placed right between VIN and PGND, and very close to the device for best decoupling effect 3. Difference values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210 and 0603 4. Smaller capacitance value, closer to device VIN pin(s) - better high frequency noise absorbing
Fig. 64
1. Connect output inductor to SiC45x with large plane to
Step 2: V
lower the resistance
IN Pin
2. If any snubber network is required, place the components on the bottom side as shown above A plane GND V decouple cap IN
Fig. 63
1. VIN (pin 23) is the input pin for both internal LDO and tON block. tON time varies based on input voltage. It is necessary to put a decouple cap close to this pin S21-0213-Rev. B, 08-Mar-2021
44
Document Number: 77863 For technical questions, contact: powerictechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000