Datasheet UF3SC120040B7S (UnitedSiC) - 10

FabricanteUnitedSiC
Descripción1200V-35mW SiC FET
Páginas / Página10 / 10 — 1000. 400. 900. 350. J). 800. (. m. 300. y. 700. gren. 600. Etot. 250. ). …
Formato / tamaño de archivoPDF / 438 Kb
Idioma del documentoInglés

1000. 400. 900. 350. J). 800. (. m. 300. y. 700. gren. 600. Etot. 250. ). E. C. g. Eon. 500. n. ni. (. 200. h. Eoff. r. 400. V. Qr. GS. =. -5V/12V,. RG_ON. =. 8.5W,. 150. VDS. =. 800V,. IS. =. 40A,. Switc. 300

1000 400 900 350 J) 800 ( m 300 y 700 gren 600 Etot 250 ) E C g Eon 500 n ni ( 200 h Eoff r 400 V Qr GS = -5V/12V, RG_ON = 8.5W, 150 VDS = 800V, IS = 40A, Switc 300

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1000 400 900 350 J) 800 ( m 300 y 700 gren 600 Etot 250 ) E C g Eon 500 n ni ( 200 h Eoff r 400 V Qr GS = -5V/12V, RG_ON = 8.5W, 150 VDS = 800V, IS = 40A, Switc 300 RG_OFF = 22W, FWD: same device di/dt = 2400A/ms, 100 200 with VGS = -5V, RG = 22W VGS = -5V, RG =10W 100 50 0 0 0 25 50 75 100 125 150 175 0 25 50 75 100 125 150 175 Junction Temperature, T Junction Temperature, T J (°C) J (°C) Figure 21. Clamped inductive switching energy vs. Figure 22. Reverse recovery charge Qrr vs. junction junction temperature at VDS = 800V and ID = 35A temperature Applications Information SiC FETs are enhancement-mode power switches formed by a high- Information on all products and contained herein is intended for voltage SiC depletion-mode JFET and a low-voltage silicon MOSFET description only. No license, express or implied, to any intellectual connected in series. The silicon MOSFET serves as the control unit property rights is granted within this document. while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with UnitedSiC assumes no liability whatsoever relating to the choice, standard gate drivers and offers superior performance in terms of low selection or use of the UnitedSiC products and services described on-resistance (R herein. DS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com. Disclaimer UnitedSiC reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. UnitedSiC assumes no responsibility or liability for any errors or inaccuracies within. Datasheet: UF3SC120040B7S Rev. A, December 2020 10