Datasheet MAX20343, MAX20344 (Maxim) - 10

FabricanteMaxim
DescripciónUltra-Low Quiescent Current, Low Noise 3.5W Buck-Boost Regulator
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Electrical Characteristics (continued). PARAMETER. SYMBOL. CONDITIONS. MIN. TYP. MAX. UNITS. Note 1:. Note 2:. Note 3:. Note 4:. Note 5:. Note 6:

Electrical Characteristics (continued) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Note 1: Note 2: Note 3: Note 4: Note 5: Note 6:

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MAX20343/MAX20344 Ultra-Low Quiescent Current, Low Noise 3.5W Buck-Boost Regulator
Electrical Characteristics (continued)
(VIN = +1.8V to +5.5V, CIN = 5µF, COUT = 8µF, TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C, VIN = +3.7V, L = 1μH, Limits are 100% tested at TA = +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SDA, EN, SCL, FAST V Input Logic High IO_IH 1.4 V SDA, EN, SCL, FAST V Input Logic Low IO_IL 0.4 V SDA, INT, PGOOD, INGOOD Output Logic VIO_OL IOL = 4mA 0.4 V Low MAX20343B/E/F/G/I, MAX20344E 400 680 SCL Clock Frequency fSCL kHz All other versions 680 Bus Free Time Between STOP and START tBUF 0.75 µs Condition START Condition t (Repeated) Hold Time HD_STA (Note 5) 0.35 µs Low Period of SCL t Clock LOW 0.75 µs High Period of SCL t Clock HIGH 0.35 µs Setup Time for a Repeated START tSU_STA 0.35 µs Condition Data Hold Time tHD_DAT (Note 6) 0 0.53 µs Data Setup Time tSU_DAT 100 ns Setup Time for STOP t Condition SU_STO 0.35 µs Spike Pulse Widths Suppressed by Input tSP 50 ns Filter
Note 1:
All devices are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.
Note 2:
Output power across the input operating voltage range is limited by input current. Refer to TOC03 for details on how the power limit changes with VIN.
Note 3:
The parameter is not production tested and values are generated through characterization only.
Note 4:
Operation down to 2.7V is supported with the integrator disabled, but stability is only guaranteed up to 1.75W output power. Beyond 1.75W, oscillations could occur unless output capacitance is increased.
Note 5:
fSCL must meet the minimum clock low time plus the rise/fall times.
Note 6:
The maximum tHD_DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal. www.maximintegrated.com Maxim Integrated | 10 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 16-BUMP WLP 12-Pin FC2QFN Electrical Characteristics Electrical Characteristics (continued) Typical Operating Characteristics Typical Operating Characteristics (continued) Pin Configurations I2C-Controlled WLP Single-Pin-Enabled WLP I2C-Controlled FC2QFN Single-Pin-Enabled FC2QFN Pin Description Pin Description (continued) Functional Diagram Functional Diagram Detailed Description Startup Voltage Architectural Description Switching Phases Buck-Boost Mode Buck-Only Mode Inductor Peak and Valley Current Limits Integrator Control Loop Disable Input Operating Voltage Output Operating Power and Other Optimizations Device Control I2C-Controlled Single-Pin-Enabled Dynamic Voltage Scaling (DVS) RSEL Voltage Setting Register Map MAX20343/MAX20344 Register Details ChipID (0x00) BBstCfg0 (0x01) BBstVSet (0x02) BBstISet (0x03) BBstCfg1 (0x04) Status (0x05) Int (0x06) Mask (0x07) LockMsk (0x50) LockUnlock (0x51) Applications Information Input and Output Capacitance Inductor Selection Soft-Start I2C Interface Slave Address Start, Stop, and Repeated Start Conditions Bit Transfer Single-Byte Write Burst Write Single Byte Read Burst Read Acknowledge Bits Register Values Typical Application Circuits Optical Heart Rate LED Supply LPWAN Radio Supply Ordering Information Revision History