Datasheet ADGS1414D (Analog Devices) - 5

FabricanteAnalog Devices
DescripciónSPI, 1.5 Ω RON, ±15 V/±5 V/+12 V, High Density Octal SPST Switch
Páginas / Página28 / 5 — Data Sheet. ADGS1414D. ±5 V DUAL SUPPLY. Table 2. Parameter. +25°C −40°C …
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Data Sheet. ADGS1414D. ±5 V DUAL SUPPLY. Table 2. Parameter. +25°C −40°C to +85°C. −40°C to +125°C. Unit. Test Conditions/Comments

Data Sheet ADGS1414D ±5 V DUAL SUPPLY Table 2 Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

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Data Sheet ADGS1414D ±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2. Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments
ANALOG SWITCH Analog Signal Range VDD to VSS V On Resistance, RON 3.3 Ω typ VS = ±4.5 V, IS = −10 mA, see Figure 29 4 4.9 5.4 Ω max VDD = +4.5 V, VSS = −4.5 V On-Resistance Match Between 0.13 Ω typ VS = ±4.5 V, IS = −10 mA Channels, ∆RON 0.35 0.43 0.45 Ω max On-Resistance Flatness, RFLAT (ON) 0.9 Ω typ VS = ±4.5 V, IS = −10 mA 1.1 1.24 1.31 Ω max LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V Source Off Leakage, IS (Off) ±0.03 nA typ VS = ±4.5 V, VD =  4.5 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Drain Off Leakage, ID (Off) ±0.03 nA typ VS = ±4.5 V, VD =  4.5 V, see Figure 32 ±0.55 ±2 ±12.5 nA max Channel On Leakage, ID (On), IS (On) ±0.05 nA typ VS = VD = ±4.5 V, see Figure 28 ±1.0 ±4 ±30 nA max DIGITAL OUTPUT Output Voltage Low, VOL 0.4 V max ISINK = 1 mA 0.3 V max ISINK = 100 µA High, VOH VL − 1.25 V V min ISOURCE = 1 mA VL − 0.125 V V min ISOURCE = 100 µA Digital Output Capacitance, COUT 4 pF typ DIGITAL INPUTS Input Voltage High, VINH 2 V min 3.3 V < VL ≤ 5.5 V 1.35 V min 2.7 V ≤ VL ≤ 3.3 V Low, VINL 0.8 V max 3.3 V < VL ≤ 5.5 V 0.8 V max 2.7 V ≤ VL ≤ 3.3 V Input Current Low, IINL or High, IINH 0.001 µA typ VIN = VGND or VL ±0.1 µA max Digital Input Capacitance, CIN 4 pF typ DYNAMIC CHARACTERISTICS1 On Time, tON 510 ns typ RL = 300 Ω, CL = 35 pF 645 680 710 ns max VS = 3 V, see Figure 37 Off Time, tOFF 280 ns typ RL = 300 Ω, CL = 35 pF 365 400 435 ns max VS = 3 V, see Figure 37 Break-Before-Make Time Delay, tD 245 ns typ RL = 300 Ω, CL = 35 pF 200 ns min VS1 = VS2 = 3 V, see Figure 36 Charge Injection, QINJ 10 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 38 Off Isolation −76 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31 Channel to Channel Crosstalk −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30 Rev. 0 | Page 5 of 28 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History Specifications ±15 V Dual Supply ±5 V Dual Supply 12 V Single Supply Continuous Current per Channel, Sx or Dx Timing Characteristics Timing Diagrams Absolute Maximum Ratings Thermal Resistance Electrostatic Discharge (ESD) Ratings ESD Ratings for ADGS1414D ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Terminology Theory of Operation Address Mode Error Detection Features Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read and Write Address Error Clearing the Error Flags Register Burst Mode Software Reset Daisy-Chain Mode Power-On Reset Applications Information System Channel Density Route Through Pins Integrated Passive Components Break-Before-Make Switching Digital Input Buffers Power Supply Rails Power Supply Recommendations 1.8 V Logic Compatibility Register Summary Register Details Switch Data Register Error Configuration Register Error Flags Register Burst Enable Register Software Reset Register Outline Dimensions Ordering Guide