Datasheet ADG1438, ADG1439 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | Serially Controlled, ±15 V/+12 V/±5 V, 8-Channel/ 4-Channel, iCMOS Multiplexers/Matrix Switches |
| Páginas / Página | 20 / 9 — Data Sheet. ADG1438/ADG1439. TIMING CHARACTERISTICS. Table 7. Parameter. … |
| Revisión | B |
| Formato / tamaño de archivo | PDF / 540 Kb |
| Idioma del documento | Inglés |
Data Sheet. ADG1438/ADG1439. TIMING CHARACTERISTICS. Table 7. Parameter. Limit at TMIN, TMAX. Unit. Test Conditions/Comments
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Data Sheet ADG1438/ADG1439 TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 3). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 7. Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments
t 2 1 20 ns min SCLK cycle time t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 5 ns min SYNC to SCLK active edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 5 ns min SCLK active edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 5 ns min SYNC rising edge to next SCLK active edge ignored t10 5 ns min SCLK active edge to SYNC falling edge ignored t 3 11 40 ns max SCLK rising edge to SDO valid t12 15 ns min Minimum RESET pulse width 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. 3 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
TIMING DIAGRAM t10 t1 t9 SCLK t2 t8 t t t7 4 3 SYNC t6 t5 DIN DB7 DB0 RESET
003
t12
08496- Figure 3. Serial Write Operation
t1 SCLK 8 16 t t t 3 9 2 t8 t4 t7 SYNC t5 t6 DIN DB7 DB0 DB7 DB0 INPUT WORD FOR DEVICE N INPUT WORD FOR DEVICE N + 1 t11 SDO DB7 DB0 UNDEFINED INPUT WORD FOR DEVICE N
004 08496- Figure 4. Daisy-Chain Timing Diagram Rev. B | Page 9 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY ±5 V DUAL SUPPLY CONTINUOUS CURRENT PER CHANNEL TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION SERIAL INTERFACE INPUT SHIFT REGISTER POWER-ON RESET DAISY-CHAINING OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADG1438/ADG1439 TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 3). VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.1
Table 7. Parameter Limit at TMIN, TMAX Unit Test Conditions/Comments
t 2 1 20 ns min SCLK cycle time t2 9 ns min SCLK high time t3 9 ns min SCLK low time t4 5 ns min SYNC to SCLK active edge setup time t5 5 ns min Data setup time t6 5 ns min Data hold time t7 5 ns min SCLK active edge to SYNC rising edge t8 15 ns min Minimum SYNC high time t9 5 ns min SYNC rising edge to next SCLK active edge ignored t10 5 ns min SCLK active edge to SYNC falling edge ignored t 3 11 40 ns max SCLK rising edge to SDO valid t12 15 ns min Minimum RESET pulse width 1 Guaranteed by design and characterization, not production tested. 2 Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V. 3 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
TIMING DIAGRAM t10 t1 t9 SCLK t2 t8 t t t7 4 3 SYNC t6 t5 DIN DB7 DB0 RESET
003
t12
08496- Figure 3. Serial Write Operation
t1 SCLK 8 16 t t t 3 9 2 t8 t4 t7 SYNC t5 t6 DIN DB7 DB0 DB7 DB0 INPUT WORD FOR DEVICE N INPUT WORD FOR DEVICE N + 1 t11 SDO DB7 DB0 UNDEFINED INPUT WORD FOR DEVICE N
004 08496- Figure 4. Daisy-Chain Timing Diagram Rev. B | Page 9 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY 12 V SINGLE SUPPLY ±5 V DUAL SUPPLY CONTINUOUS CURRENT PER CHANNEL TIMING CHARACTERISTICS TIMING DIAGRAM ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION SERIAL INTERFACE INPUT SHIFT REGISTER POWER-ON RESET DAISY-CHAINING OUTLINE DIMENSIONS ORDERING GUIDE